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* ENGR00230981-1 pfuze:set all switches to PFM mode in standbyRobin Gong2012-10-26-25/+22
| | | | | | | | | | | To save power, set all switches to PFM mode in standby,although PFM mode need 6% tolerance.But it will be implemented in kernel, and move the workaround which all buck switches need be configured PWM mode on PF100 1.0 Another two change is: 1. u-boot will print PFUZE device id and revision id. 2. add value check for i2c write and read. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00221135: imx6x: clear PowerDown Enable bit of WDOG1_WMCRRobby Cai2012-08-24-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | From IC spec: --- The Power down Counter inside WDOG-1 will be enabled out of reset. This counter has a fixed time-out value of 16 seconds, after which it will drive the WDOG-1 signal low. To prevent this, the software must disable this counter by clearing the PDE bit of Watchdog Miscellaneous Control Register (WDOG_WMCR) within 16 seconds of reset de-assertion. Once disabled, this counter cannot be enabled again until the next system reset occurs. This feature is provided to prevent the hanging up of cores after reset, as WDOG-1 is not enabled out of reset. --- NOTE for the last sentence: This feature requires a dedicated WDOG_B pin for it. The fact that changing the IOMUX configuration can alter the WDOG_B functionality (GPIO by default) is not ideal as it defeats the purpose of this feature. But it still takes effect when the muxed pin is configured as WDOG_B within 16 seconds. Clear PDE bit to avoid WDOG_B (aka, WDOG-1) assertion. Tested on MX6SL. May add this for other MX6x. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00220164 pfuze:rise VDDARM_IN to 1.425V and work around pfuze1.0Robin Gong2012-08-13-0/+18
| | | | | | | | | 1.Considering pfuze tolerance and IR drop and board ripple, need rise from 1.375V to 1.425V. Only for Sabresd. 2.workaround pfuze1.0 ER1, set all buck regulator except SW1C to PWM mode. now for mx6sl_arm2 and mx6_sabresd. Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00218972 MX6 Secure Boot, Change to dynamic HAB data authenticationEric Sun2012-08-01-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original secure boot implementation make a consumption that u-boot.bin will not exceed 0x2F000. With this consumption, the hab data is hard coded in linker script file to relative address 0x2F000 without causing any problem. But when this consumption don't hold, the hard coded way will cause memory region overlap and break build. So we need to change to a dynamic way of allocating hab_data. The new implementation put hab data at the next 0x1000 alignment after u-boot data and text section, instead of hard coded to 0x2F000. Similar changes is made to uImage authentication implementation. Changes in U-Boot includes: - in u-boot.lds file, change "__hab_data" to dynamic align to 0x1000 - change authenticate_image implementation, originally the uImage parameters are hard coded, now they are retrived from the "load_addr" and the image_hdr The new secure image layout: U-Boot +-------------------+ DDR_START | | | U-Boot Image | | | +-------------------+ DDR_START + UBOOT_SIZE | PADDING | +-------------------+ align to 0x1000 | CSF Data | - +-------------------+ +-- CSF + Pad, Size : 0x2000 | PADDING | - +-------------------+ uImage +-------------------+ DDR_START | | | uImage | | | +-------------------+ DDR_START + UIMAGE_SIZE | PADDING | +-------------------+ align to 0x1000 | IVT | ---- Size : 0x20 +-------------------+ | CSF Data | - +-------------------+ +-- CSF + Pad, Size : 0x2000 | PADDING | - +-------------------+ Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00217764 MX6 Secure Boot : Fix NAND BOOT Failure due to secure patchEric Sun2012-07-23-3/+4
| | | | | | | | | | | | | | | | | | With the secure boot patch. MX6 NAND Boot is not functional. The root cause is that, the original secure boot patch fills "0xFF' to spacing regions, due to a issue in ROM code, read pages of all "0xff" will be treated as a critical error. Thus prevent the U-Boot from booting normally. The fix adjust image copy size in IVT so that when secure boot is not enabled, no unuseful data is copied by ROM code. Also the secure boot option is default disabled. The end user won't enable it unless they know what they are doing. These prevent the ROM code from copied pages of "0xff" data, and fix the issue. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00217381-01: mx6sl add sd1 and sd2 to support SD3.0Ryan QIAN2012-07-19-2/+2
| | | | | | enable SD3.0 support on SD1 and SD2 on mx6sl arm2 cpu board. Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00217114-1 MX6 U-Boot, Secure Boot, one code base for MX6Q/DL/SLEric Sun2012-07-13-0/+24
| | | | | | | | Move the secure boot related implementation code from mx6q_arm2.c to mx6/generic.c. In this way the HAB feature can be shared by all MX6 platforms Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00216852 MX6SL ARM2, UBoot : Apply V0.93 LPDDR2 ScriptEric Sun2012-07-13-17/+20
| | | | | | | | IC Validation team release new LPDDR2 script V0.93 in the following link, "http://compass.freescale.net/livelink/livelink?func=ll&objId=226733834/" Make changes to align to it Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00215197 pfuze MX6SL_ARM2: enable LDO bypass on u-bootimx-android-r13.5-alphaRobin Gong2012-07-04-0/+313
| | | | | | 1.enable I2C and I2C bus recovery support on mx6sl_arm2 2.enable LDO bypass on u-boot, by configuring 'CONFIG_MX6_INTER_LDO_BYPASS' Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00214866 MX6SL ARM2, UBoot : Apply V0.91 LPDDR2 ScriptEric Sun2012-06-26-463/+397
| | | | | | | | | | | Validation team released lateset LPDDR2 script V0.91, See "http://compass.freescale.net/livelink/livelin k?func=ll&objId=226435628&objAction=browse&viewType=1" This change is necessary for bus freq scaling Apply it for both DCD mode and plugin mode. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00210918-1 android: add mx6sl android supportZhang Jiejing2012-05-29-0/+33
| | | | | | | | | | - add android build config for mx6sl_arm2 board. - add gpio support for mx6sl - add boot image support - add android recovery support - add fastboot support, but fastboot cannot transfer file. Signed-off-by Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00181337-4 i.mx6 : i.mx6sl: Fix FEC RX CRC ErrorEric Sun2012-05-03-1/+10
| | | | | | | | | | | Since FEC_RX_ER is not connected with PHY(LAN8720A), we need either configure FEC_RX_ER PAD to other mode than FEC_RX_ER, or configure FEC_RX_ER PAD to FEC_RX_ER but need pull it down, otherwise, FEC MAC will report CRC error always. We configure FEC_RX_ER PAD to GPIO mode here and remove the SW hack which ignore the CRC error in fec driver Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00181337-3 i.mx6: i.mx6sl: add initial support for i.mx6sl ARM2 boardEric Sun2012-05-03-0/+1776
This patch is to add the initial support for i.mx6sl ARM2 board, the patch does: - implemention of LPDDR2 init script - Plug-in/DCD mode support to do DDR initialization - Debug UART(UART1) support - SPI-NOR(M25P32, 4MB) flash support - FEC support, PHY(LAN8720A, RMII mode) - SD/MMC card support, SD1/SD2/SD3 Signed-off-by: Danny Nold <dannynold@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Nancy Chen <Nancy.Chen@freescale.com> Signed-off-by: Eric Sun <jian.sun@freescale.com>
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