| Commit message (Collapse) | Author | Age | Lines |
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Currently mx6qpsabresd board file only add PHY AR8031 gpio reset
in non-DM driver, then net DM driver PHY cannot work after stress
reboot test. So also add gpio reset for DM driver.
RGMII and PHY work at VDDIO 1.8V has better timing and to align
the IO voltage with kernel, also set the IO voltage to 1.8V.
Since i.MX6QP tx_clk can loop from SOC internal, no need to set
PHY output 125Mhz clock that can save power.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
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* Add API to read\write MISC partition.
* get the boot mode from BCB command when boot up.
* get the boot up tactics from bootctrl.
Change-Id: Icbba6340e10983dddc1b04804ecc012a3a3c57d0
Signed-off-by: zhang sanshan <sanshan.zhang@nxp.com>
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Use CONFIG_DM_USB to comment out USB setup functions used by non-DM driver. So
they won't be executed when using DM driver.
These USB setup functions may setup power control pins to USB_PWR function not GPIO,
which is different as the GPIO function used by USB vbus-supply. And cause the power control
not work.
Signed-off-by: Ye Li <ye.li@nxp.com>
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VGEN3 and VGEN5 have been fused the right value in PF0100 on i.mx6qp board,
so software didn't need to change their voltage output anymore. Otherwise,
VGEN3 will be wrongly updated from 1.8v to 2.8v.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
(cherry picked from commit 6f7f185664a401f03f6ce6c81b996c1f27fdbe73)
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add board level support for android fastboot feature. Each board has
a android specified header file for defining android related configuraitons.
And add build targets for their android uboot images building.
For mx6qsabreauto, mx6sabresd and mx7dsabresd, we enable the android
fastboot exclusive with DFU.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 43fe988af28c5e51fb23aa846e04bc9698256926)
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We found a issue in PLL6 ENET that changing the bit[1:0] DIV_SELECT for ENET
ref clock will impact the SATA ref 100Mhz clock. If SATA is initialized before
this changing, SATA read/write can't work after it. And we have to re-init SATA.
The issue can reproduce on both i.MX6DQP and i.MX6DQ. IC investigation is ongoing.
This patch is an work around that moves the ENET clock setting
(enable_fec_anatop_clock) from ethernet init to board_init which is prior
than SATA initialization. So there is no PLL6 change after SATA init.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit fd8fbf7fa0b10199ac89cd13cae851149f51accb)
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In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY,
While kernel uses the clock from internal PLL by setting GPR5 bit 9.
When doing warm reset in kernel, the GPR regigster is not reset, so
the clock source still is the PLL. This causes ENET in u-boot can't work.
In this patch, we change the u-boot to use internal PLL to align with
kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 7f00c72e17e4e440df62aa4945a619fdbc9cfd8f)
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Set the ID pin pad to pull up not the pull down at default, otherwise
we can't enter the device mode, but always detect as host.
After this change we have to use portA cable to play as host,
and use portB cable for device.
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit b315d6b36a913d75d25284320e69050ebdf7a7eb)
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CONFIG_SECURE_BOOT is used for signed image building, this configuration is
not enabled at default. Comment it in mx6/mx7 common header file. Users can
uncomment it to enable.
Also add CONFIG_CSF_SIZE for defining the CSF reserved size and resize
the CONFIG_CSF_SIZE to 0x4000 to align with v2016.03.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 01cc7d9bc205251c13712418d51f3a4d7b20861b)
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Port LDO bypass support from v2015 to support the features:
1. Add check for 1.2GHz core speed. If Speed grading fuse is for 1.2GHz,
enable LDO bypass and setup PMIC voltages. LDO bypass is dependent
on the flatten device tree file.
2. We set WDOG_B in set_anatop_bypass() before, because it is the only case, but now
on i.mx6sabreauto board, we didn't use ldo-bypass mode, but have to use WDOG_B to
reboot whole board, so split these code to independent function so that board file
can call it freely.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5b87d04dba66fa45375d59648838ef89f559f75d)
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Align board code and header file with imx_v2016.03.
Update pmic settings for i.MX6QP.
wrap spi code together using CONFIG_MXC_SPI macro.
To i.MX6SOLO, need to define nosmp in bootargs.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit bb35d09d140efc7ff9b74bbcd77d7827c1dd503e)
Signed-off-by: Ye Li <ye.li@nxp.com>
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DDR script file:
arik_r2_sdb_ddr3_528_1.14.inc
Compass link:
http://compass.freescale.net/livelink/livelink?func=ll&objid=235302593&objAction=browse&sort=name&viewType=1
Update:
setmem /32 0x020e0534 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 (SDQS0_B_TRIM=01, SDQS0_TRIM=10)
setmem /32 0x020e0538 = 0x00008000 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 (SDQS1_B_TRIM=00, SDQS1_TRIM=00)
setmem /32 0x020e053C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 (SDQS2_B_TRIM=01, SDQS2_TRIM=10)
setmem /32 0x020e0540 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 (SDQS3_B_TRIM=01, SDQS3_TRIM=10)
setmem /32 0x020e0544 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 (SDQS4_B_TRIM=01, SDQS4_TRIM=10)
setmem /32 0x020e0548 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 (SDQS5_B_TRIM=01, SDQS5_TRIM=10)
setmem /32 0x020e054C = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 (SDQS6_B_TRIM=01, SDQS6_TRIM=10)
setmem /32 0x020e0550 = 0x00018200 // IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 (SDQS7_B_TRIM=01, SDQS7_TRIM=10)
setmem /32 0x021b08c0 = 0x24912489 // fine tune SDCLK duty cyc to low - seen to improve measured duty cycle of i.mx6
setmem /32 0x021b48c0 = 0x24914452
setmem /32 0x021b0018 = 0x00011740 // MMDC0_MDMISC, RALAT=0x5, WALAT=0x1
Test:
Passed stress memtester on one board.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit b7f43f47a78c9d0c14fe104daf22efab13709ab1)
(cherry picked from commit f521de2c5b79ab7f9b60b26cbe6a7ad50cfce9fa)
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Align ddr script with imx_v2016.03 latest ddr script.
mx6qp.cfg is 1.13 version
http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/8111e4d0cd81226899be637013048281e3c097b4
http://compass.freescale.net/livelink/livelink?func=ll&objId=234753630&objAction=browse&viewType=1
arik_r2_sabre_ddr3_528_1.13.inc is for sabre-AI
arik_r2_sdb_ddr3_528_1.13.inc is for sabresd
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 39c2989e6ba0de6b35b2d93acd9d67f889ab4b39)
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Since there is already CONFIG_MX6S used for i.MX6 SOLO in u-boot codes,
we don't need to add new CONFIG_MX6SOLO. Rename the existing CONFIG_MX6SOLO
to CONFIG_MX6S.
Additional, for CONFIG_MX6S, we should select CONFIG_MX6DL. The major difference
for these two chips are core number and DDR controller. So all duallite
relevant definitions can apply to solo. User can combine the two configs
if any code only apply to solo or duallite.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add plugin.S for plugin boot initialization on mx6dq/dl/dqp sabresd and sabreauto
boards. Need to set "CONFIG_USE_IMXIMG_PLUGIN" for this feature.
Add the configurations for the plugin enabled buiding.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Dynamic setting mmcdev and mmcroot for mx6sabresd and mx6qsabreauto.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 14040e07549a394500c11e815f31299e4fb0ac50)
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Support epdc for mx6dlsabresd board.
Introduce a new configuration file mx6dlsabresd_epdc_defconfig.
Add related settings.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 467974ffda4b874e16f0c84974c3d65d85f84f6a)
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As the HDMI splash screen feature is not well supported,
we should not set it to be the default display. In case,
users leave the 'panel' uboot environment variable empty
and connect the board with a HDMI monitor, the HDMI detect
funtion will work and enable the HDMI splash screen. So,
this patch disables HDMI detect function so that users
may only explicitly set the 'panel' variable to be 'HDMI'
to use HDMI splash screen.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit d482c54a9fbf458fdb2270cf990d8ec727823bb1)
(cherry picked from commit b484d36882c8db9ddb8262001cfef187a28051b2)
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-Change HDMI video mode to VGA.
-Add pixel clock fraction part setting in IPU driver,
fix video mode timing issue.
-Add overflow state clear workaround,
fix kernel hang in HDMI driver issue.
-Correct IPU clock to 264MHz.
Signed-off-by: Sandor Yu <R01008@freescale.com>
Signed-off-by: Nitin Garg <nitin.garg@freescale.com>
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 5028519b434d5dfbe53c48ac4b115ff8b69bbac7)
(cherry picked from commit 8dcbd43b971616fb67dc3b2af32e2d33f68ed0ce)
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Modify and remove configurations conflicts with DM drivers from head file.
Enable DM drivers and OF_CONTROL in defconfig.
Also update the GPIO usage to call gpio_request before any gpio using, and
update power_init_board since the PMIC APIs are changed in Pfuze DM driver.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Since commit ce412b79e7255770 ("drivers: net: phy: atheros: add separate
config for AR8031") ethernet does not work on mx6sabresd.
This commit correctly assigns ar8031_config() as the configuration
function for AR8031 in the same way as done in the Linux kernel.
However, on mx6sabresd design we need some additional configuration,
such as enabling the 125 MHz AR8031 output that needs to be done
in the board file.
This also aligns with the same method that the kernel performs
the AR8031 fixup in arch/arm/mach-imx/mach-imx6q.c.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
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Fixed typo for doc/README.imximage on respective imximage.cfg files.
Cc: Tom Rini <trini@konsulko.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
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Add a README to explain the steps for booting mx6sabresd in different ways:
1. Booting via Normal U-Boot (u-boot.imx)
2. Booting via SPL (SPL and u-boot.img)
3. Booting via Falcon mode (SPL launches the kernel directly)
Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
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Allow i.MX6Q Sabre SD to load the kernel and dtb via SPL in Falcon mode.
Based on the Falcon mode code for MX6 Gateworks Ventana board.
Signed-off-by: Diego Dorta <diego.dorta@nxp.com>
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When using SPL on i.mx6 we frequently notice some DDR initialization
mismatches between the SPL code and the non-SPL code.
This causes stability issues like the ones reported at 7dbda25ecd6d7c
("mx6ul_14x14_evk: Pass refsel and refr fields to avoid hang") and also:
http://lists.denx.de/pipermail/u-boot/2016-September/266355.html .
As the non-SPL code have been tested for long time and proves to be reliable,
let's configure the DDR in the exact same way as the non-SPL case.
The idea is simple: just use the DCD table and write directly to the DDR
registers.
Retrieved the DCD tables from:
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
and
board/freescale/mx6sabresd/mx6qp.cfg
(NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga)
This method makes it easier for people converting from non-SPL to SPL code.
Other benefit is that the SPL binary size is reduced from 44 kB to 39.9 kB.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
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Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
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Currently MX6 SPL DDR initialization hardcodes the REF_SEL and
REFR fields of the MDREF register as 1 and 7, respectively for
DDR3 and 0 and 3 for LPDDR2.
Looking at the MDREF initialization done via DCD we see that
boards do need to initialize these fields differently:
$ git grep 0x021b0020 board/
board/bachmann/ot1200/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/ccv/xpress/imximage.cfg:DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x7800
board/freescale/mx6qarm2/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qarm2/imximage_mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6dl.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6qsabreauto/mx6qp.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6dlsabresd.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg:DATA 4 0x021b0020 0x00005800
board/freescale/mx6slevk/imximage.cfg:DATA 4 0x021b0020 0x00001800
board/freescale/mx6sxsabreauto/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/freescale/mx6sxsabresd/imximage.cfg:DATA 4 0x021b0020 0x00000800
board/warp/imximage.cfg:DATA 4 0x021b0020 0x00001800
So introduce a mechanism for users to be able to configure
REFSEL and REFR fields as needed.
Keep all the mx6 SPL users in their current REF_SEL and REFR values,
so no functional changes for the existing users.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Eric Nelson <eric@nelint.com>
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Currently the LVDS backlight does not work in U-Boot after a “reboot” comand
in the kernel.
This problem occurs because the kernel uses this pin in PWM mode and U-Boot
does not configure the backlight pin as GPIO functionality.
So fix the problem by explicitly configuring the backlight pin as GPIO in
U-Boot.
Signed-off-by: Marco Franchi <marco.franchi@nxp.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Tested-by: Fabio Estevam <fabio.estevam@nxp.com>
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Use simpler runtime cpu dection macros.
Signed-off-by: Peng Fan <van.freenix@gmail.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
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enable_lvds() function only set bits IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT and
IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT, but these bits were already set
previously inside setup_display().
We can safely remove enable_lvds() then.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
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VESA 1024x768 results in much more accurate timings.
Based on the patch from Soeren Moch for the tbs2910 board.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
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Correct spelling of "U-Boot" shall be used in all written text
(documentation, comments in source files etc.).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
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Implement board_mmc_get_env_dev for the boards.
Following is examples:
SD1/SD2/SD3: return devno;
SD2/SD3: return devno - 1;
SD2/SD4: if (devno == 2), return dev - 2; return dev - 1;
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
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The BOOTCFG value used by bmode for SABRESD eMMC boot are actually for SD card.
Fixed the value to correct one.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Fabio Estevam <fabio.estevam@nxp.com>
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Update my email address to the NXP account.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
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As per the AR8031 datasheet:
"For a reliable power on reset, suggest to keep asserting the reset
low long enough (10ms) to ensure the clock is stable and clock-to-reset
1ms requirement is satisfied."
So do as suggested and also add a 100us delay after deasserting the
reset line to guarantee that the PHY ID can be read correctly and the
Atheros 8031 PHY driver can be loaded automatically.
This results in a simpler code.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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There is really no need to provide an empty reset_cpu() implementation,
so just remove it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
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Add i.MX6DQP-Sabresd board support:
1. set fdt_file according to board_rev which is set at runtime.
2. Add mx6dqp_ddr_ioregs and calibration value for this board.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
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Remove duplicated SYS_SOC Kconfig entry from board Kconfig,
because we have this entry in arch/arm/cpu/armv7/mx6/Kconfig.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Heiko Schocher <hs@denx.de>
Cc: Christian Gmeiner <christian.gmeiner@gmail.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Troy Kisky <troy.kisky@boundarydevices.com>
Cc: Nikita Kiryanov <nikita@compulab.co.il>
Cc: "Eric Bénard" <eric@eukrea.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Markus Niebel <Markus.Niebel@tq-group.com>
Cc: Otavio Salvador <otavio@ossystems.com.br>
Acked-by: Stefan Roese <sr@denx.de>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Acked-by: Markus Niebel <Markus.Niebel@tq-group.com>
Acked-by: Troy Kisky <troy.kisky@boundarydevices.com>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
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To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg
to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper.
The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg
when ddr_type is for DDR3. Later we can use ddr_type to initialize
MMDC for LPDDR2.
Initialize ddr_type for different boards which enable SPL.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Tim Harvey <tharvey@gateworks.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Reviewed-by: Stefan Roese <sr@denx.de>
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Detect the SOC and board variant at runtime and change the dtb name,
but not hardcoding the fdt_file env variable.
Take the following patch as a reference.
Íd58699b157df75f1aa0b363ea9c21add21a0c
"mx6cuboxi: Load the correct 'fdtfile' variable"
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Stefano Babic <sbabic@denx.de>
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The variable 'ret' is used to store the value returned by pfuze_mode_init(),
so it should of type 'int' instead of 'unsigned int' in order to correctly
handle negative numbers.
Fix the variable type.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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RTT_NOM_120OHM is not defined, so remove its ifdef.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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mx6sabresd has four MT41K128M16JT-125 chips. Each memory has 16-bit bus
and 2GiB, so fix the width and density fields accordingly.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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To normal mode, use APS switching mode.
To standy mode, use PFM switching mode.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
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Add pinmux settings, implement board_ehci_hcd_init and board_ehci_power
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Modify the pfuze init for mx6sabresd to use the shared
"pfuze_common_init" function. And move this initialization to
power_init_board.
Signed-off-by: Ye.Li <B37916@freescale.com>
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In U-boot it is preferred to access the register via structure pointer, so
convert it such style.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Let's add mx6sabresd_spl_defconfig entry into MAINTAINERS, so that we avoid
getting a warning that the mx6sabresd_spl is not maintained.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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Make clear that current SPL code only supports the mx6q variant.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
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