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Update ddr script to version 1.07:
1. Change MDCCR from default value to 0x24912492,
it will improve DDR duty cycle
2. The MMDC reorder bypass option, which has better DRAM performance
URL:
http://compass.freescale.net/livelink/livelink?func=ll&objId=234335046&objAction=browse&viewType=1
Test Results:
3 boards passed 48 hours memtester stress test.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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Update to 1.05 ddr script, url:
http://compass.freescale.net/livelink/livelink?func=ll&
objId=233944823&objAction=browse&viewType=1
File name:
arik_r2_sabre_ddr3_528_1.05c.inc
Update:
Read latency
Aging control for IPU1/PRE0/PRE3
Aging control for IPU2/PRE1/PRE2
Test results:
3 boards passed overnight memtester stress test.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit b8625b732cfc59e44955f0e23b581e7896be1733)
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1. Add DDR script v1.04 for i.MX6DQP SABREAUTO board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e0b316f071aa17c8e41a50f395346ab9f012e665)
Conflicts:
board/freescale/mx6qsabreauto/mx6qsabreauto.c
boards.cfg
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Add plugin support
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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