| Commit message (Collapse) | Author | Age | Lines |
|---|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Update IPU QoS settings from 0x007f007f to 0x77177717
according to the SoC team's recommendation. This change
should be able to balance AXI ID0/2/3 priority and set
AXI ID1 priority relatively lower, which matches the way
we use AXI ID0/1/2/3 for IDMAC23(0), regular IDMACs,
IDMAC27 and IDMAC28 respectively in kernel. The specific
priority values for each AXI ID are supposed to be picked
for the sake of an overall good system performance.
Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
(cherry picked from commit 7c4bee613dc47c9e2fb147a159236bca04b8618b)
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Update to 1.05 ddr script, url:
http://compass.freescale.net/livelink/livelink?func=ll&
objId=233944823&objAction=browse&viewType=1
File name:
arik_r2_sabre_ddr3_528_1.05c.inc
Update:
Read latency
Aging control for IPU1/PRE0/PRE3
Aging control for IPU2/PRE1/PRE2
Test results:
3 boards passed overnight memtester stress test.
Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
(cherry picked from commit b8625b732cfc59e44955f0e23b581e7896be1733)
|
|
|
1. Add DDR script v1.04 for i.MX6DQP SABREAUTO board.
2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9]
and init the enet pll output to 125Mhz.
3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN.
Build target: mx6qpsabreauto_config
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Robin Gong <b38343@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit e0b316f071aa17c8e41a50f395346ab9f012e665)
Conflicts:
board/freescale/mx6qsabreauto/mx6qsabreauto.c
boards.cfg
|
