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* mx53loco: Fix boot hang during reboot stress testFabio Estevam2015-02-10-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently by running the following test: => setenv bootcmd reset => save => reset , we observe a hang after approximately 20-30 minutes of stress reboot test. Investigation of this issue revealed that when a single DDR chip select is used, the hang does not happen. It only happens when the two chip selects are active. MX53 reference manual states at "28.6.2 Memory ZQ calibration sequence": "The controller must keep the memory lines quiet (except for CK) for the ZQ calibration time as defined in the Jedec (512 cycles for ZQCL after reset, 256 for other ZQCL and 64 for ZQCS)." According to the SDE_0 and SDE_1 bit descriptions from register ESDCTL_ESDCTL: "Writing 1 to SDE0 or SDE1 will initiate power up delays as JEDEC defines. Power up delays are a function of the configured memory type (DDR2/DDR3/LPDDR2)" So make sure to activate one chip select at time (CS0 first and then CS1 later), so that the required JEDEC delay is respected for each chip select. With this change applied the board has gone through three days of reboot stress test without any hang. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* Fix references to the documentation filesAnatolij Gustschin2013-05-10-1/+1
| | | | | | | | | | | | Many boot image configuration files refer to the appropriate documentation file, but these references contain typos in the directory and file name. Fix them. Also fix reference to doc/README.SPL file. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Prafulla Wadaskar <prafulla@marvell.com> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
* imximage.cfg: run files through C preprocessorTroy Kisky2013-01-22-40/+43
| | | | | | | | | | | | The '#' used as comments in the files cause the preprocessor trouble, so change to /* */. The mkimage command which uses this preprocessor output was moved to arch/arm/imx-common/Makefile .gitignore was updated to ignore .cfgtmp files. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
* MX53: DDR: Fix ZQHWCTRL field TZQ_CSTroy Kisky2012-04-16-1/+1
| | | | | | | | | Currently, board files are setting this field to 0x01 which the manual says is a reserved value. Change to use the default of 0x02 - 128 cycles. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Acked-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx53: ddr3: Update DD3 initializationFabio Estevam2011-09-04-3/+3
| | | | | | | | | | | Updated mx53 ddr3 script in order to align with the latest Freescale version from July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This changes write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX53: support for freescale MX53LOCO boardJason Liu2011-05-23-0/+96
This patch add initial support for freescale MX53LOCO board. Network(FEC),SD/MMC,UART have been supported by this patch Signed-off-by: Jason Liu <jason.hui@linaro.org>