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* ENGR00156389: turn off child clocks before reconfigure perclk_rootTerry Lv2011-09-13-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | In addition to ensuring that PERCLK remains at least 2.5 times slower than the AHB clock, certain steps need to be followed to ensure robust operation of PERCLK when reconfiguring the PERCLK clock source. To properly configure the PERCLK clock source, the following steps are required: 1.In the CCGR registers, gate the clocks to all PERCLK-dependent modules. 2.Select the desired input clock for the PERCLK root clock (to be either source from the peripherals main source clock or the lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel bit. 3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers to the desired setting. Refer to the CBCDR register for details. 4.In the CCGR registers, enable the desired clocks for the PERCLK-dependent module clocks. Certain steps are required to reconfigure perclk_root. If don't follow these steps, GPT timer may stop and the kernel stops at " "Calibrating delay loop". Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00156098 mx53_smd/mx53_loco: DA9053 I2C SDA stuck low issue on bootupWayne Zou2011-09-06-1/+102
| | | | | | | | | | | | | | | | For DA9053 I2C SDA stuck low issue: the I2C block in DA9053 may not correctly receive a Power On Reset and device is in unknown state during start-up. The only way to get the chip into known state before any communication with the Chip via I2C is to dummy clock the I2C and bring it in a state where I2C can communicate. Dialog suggested to provide 9 clock on SCL. Dialog don't know the exact reason for the fault and assume it is because some random noise or spurious behaviour. This has to been done in host platform specific I2C driver during start-up when the I2C is being configured at platform level to supply with dummy 9 clock on SCL. Dialog I2C driver has no control to provide dummy 9 clock on SCL. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00139254: Enable MX6Q Uboot Splash ScreenSandor Yu2011-09-02-0/+8
| | | | | | | | | | | | | | Only support LVDS0 splash screen. Enable splash process: 1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2.Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Sandor Yu <r01008@freescale.com>
* ENGR00155283: Set dpgdck0_2_en to 0 when freq is lower than 300MHzTerry Lv2011-09-01-2/+10
| | | | | | | | 1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz. 2. When dpgdck0_2_en is 0, the formula to calculate output freq will be changed to 2 * freq * []. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00154666-2: Align u-boot mmc command with communityTerry Lv2011-09-01-1/+1
| | | | | | Trivial change to remove build warnings. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155284 mx53_smd: move I2C access to board_init_late for system hang issueWayne Zou2011-08-31-9/+12
| | | | | | | | | | | | MX53 SMD hangs if reset many times with lower possibility. If doing I2C access in early time, I2C may cause system hangs. So moving I2C access to late phase to make system hang issue disappear. QA Test result: QA raised 6 full rounds of CTS one-round test Totally ran for 6 rounds about 27 hours, reboot for 56*6=336 times, no reboot failure occurred. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00154672: Change to use rom plugins for mx53 boardsTerry Lv2011-08-29-80/+200
| | | | | | | | | | | | | 1. As customer required, we change to use rom plugins for mx53 boards. Tested pass with latest mfg tools. 2. Update DDR3 script based on MX53_TO2_DDR3_LCB_SMD_ARDb_v2.inc. Got from http://compass.freescale.net/livelink/livelink?func=ll &objId=221058910&objAction=browse&viewType=1. 3. Fix a tiny build error in mx53_smd.c. This error will happen when building mx53_smd_mfg. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155240 mx53_smd: Fix a bug that hangs on printf() in board_initWayne Zou2011-08-23-5/+1
| | | | | | remove printf() because serial interface is not ready in board_init() Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00155138 mx53_smd/mx53_loco: Add i2c retry to fix DA9053 i2c NAK issueWayne Zou2011-08-22-1/+10
| | | | | | | | | when board boots up, during the iMX53 SOC does DA9053 Read/Write operation, it writes slave address and wait for ACK . Instead of ACK PMIC sends NAK. A workaround fix is provided as a part of retries to fix I2C NAK for very first access. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00151310 mx53 smd: force warm reset as cold resetLily Zhang2011-07-22-0/+9
| | | | | | | | | | This patch is used to support watchdog timeout in SMD RevA, RevB board. 1. Revert "ENGR00143469 mx53 smd: pull down GPIO_9 to reset the board". 2. Force warm reset as cold reset. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00151695 mx53 ddr3: update ESDREF and MR0Lily Zhang2011-07-21-3/+3
| | | | | | | | | | | Updated mx53 ddr3 script according to MX53_TO2_DDR3_LCB_SMD_ARDb_v1.inc from Michael J Kjar on July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This chagned write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00151187 MX53 SMD: Kernal stopped Usb driver after reseting in stop modeWayne Zou2011-06-10-1/+14
| | | | | | | After reseting in stop mode, the VUSB_2V5 voltage is disable by pmic. It needs to be enable manually in u-boot. Signed-off-by: Wayne Zou <b36644@freescale.com>
* ENGR00144224: MX53: Add MMU mapping for all peripheralsTerry Lv2011-06-09-7/+16
| | | | | | | Not all peripherals are mapped in MMU. Thus we add those missed mapped area. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00143457: Don't let ROM copy .bss sectionJason Liu2011-05-16-1/+2
| | | | | | | | | | | Don't need let ROM copy the .bss section since it will all be zeroed by u-boot at start up, thus it can speed up the boot up time. Need add CONFIG_FLASH_HEADER_OFFSET to the size since ROM will copy from the beginning of the MMC card. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00142497 Android: MX53_SMD: check eMMC and SD recovery file.Zhang Jiejing2011-04-22-38/+42
| | | | | | | | | | Check eMMC and SD cards recovery file, if it exist, enter recovery mode. original code only check SD card, since we already change main storage to eMMC, so we check it both, since most of customer still test it under SD card, check them to avoid support effert. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00142322: mx53-smd: spi nor: can't erase 0x200000 sizeTerry Lv2011-04-20-1/+1
| | | | | | | | | | | | | Spi nor can't erase 0x200000 size. There are two issues in this CR. 1. Spi nor can't erase 0x200000 size. 2. Whole chip erase don't work. The solution will be: 1. Delay more time for WIP check. 2. Use normal erase for whole chip erase. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141363: change mx53 uart clk parent to pll2Jason Chen2011-03-31-3/+9
| | | | | | | | | | Change all mx53 platform uart clk default parent to pll2. MX53 SMD board need support LVDS and HDMI at the same time, they may use the same clock parent-pll4, so kernel need change ipu di clock parent to pll3, after that, uart clock parent need change to pll2 to avoid console mess. Signed-off-by: Jason Chen <b02280@freescale.com>
* ENGR00141129: Add m25p32 spi_nor support for mx53_smdTerry Lv2011-03-24-0/+81
| | | | | | Add m25p32 spi_nor support for mx53_smd. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00140982 MX53 Increase VDDGP to 1.25V for 1 GHzAnish Trivedi2011-03-22-2/+2
| | | | | | | | MX53 TO 2.0 requires 1.25V for VDDGP instead of 1.2V in order for the core to operate at 1 GHz. Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00140825: Add mx53 to2.1 chip id recognitionTerry2011-03-20-1/+4
| | | | | | Add mx53 to2.1 chip id recognition. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139747: Read fuse to distinguish between mx53 revA and revBTerry Lv2011-03-02-7/+36
| | | | | | | | | Read fuse to distinguish between mx53 revA and revB. Now SoC efuse is used for board id. Thus we now check fuse value for board rev and id. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139924 mx53 smd &loco: set bootup vdd GP to 1.2vZhou Jingyu2011-03-01-0/+3
| | | | | | set bootup vdd GP to 1.2v for mx53 smd &loco Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00138040-3 Protect splashimage related stuffs by configLiu Ying2011-01-17-1/+1
| | | | | | | This patch protects splashimge related stuffs by config option for mx51 bbg, mx53 ard and mx53 smd. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137552 MX53: increase VDDGP as 1.2V for 1GHZLily Zhang2011-01-15-1/+15
| | | | | | | | | The norminal voltage of VDDGP for 1GHZ is 1.2V in MX53 TO2.0 datasheet (RevD). So set the CPU frequency as 800MHZ firstly since VDDGP is 1.1V after power on. After increasing VDDGP as 1.2V, increase CPU as 1GHZ. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137894-6 MX53 SMD:Support splashimageLiu Ying2011-01-14-1/+127
| | | | | | | | | | | | | | This patch supports to use pwm wave to control backlight. The pwm rate is 20KHz and the pwm duty is 50%. Only lvds panel is supported. Use 'lvds_num' env variable to choose to use lvds0 or lvds1. However, only lvds1 is tested as the lvds cable cannot be plugged into lvds0 connector. Note that you need to add 'splashimage' env variable to set the memory address of the bmp image. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137604: Change PLL4 to 455MHz for mx53Terry Lv2011-01-07-1/+6
| | | | | | | Required by display to set ldb. We need to set PLL4 to 455MHz. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137642 MX53 Uboot Align DDR3 script for Loco and SMD boardsAnish Trivedi2011-01-05-2/+2
| | | | | | | | | | | | | Changed the value of one register, offset 0x88, of the ESDCTL controller to match the official script for the boards, entitled "MX53_TO2_DDR3_LCB.inc", found at http://compass.freescale.net/livelink/livelink/221435668/ MX53_TO2_DDR3_LCB.inc.txt?func=doc.Fetch&nodeid=221435668 The register value sets read delay lines. The change is minor. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00136075 MX53: Add SMD board supportLily Zhang2010-12-30-0/+1236
Add MX53 SMD support: - Use DDR3 script for SMD board from Mike Kjar: "Rita_init_LCB_CMOS.inc" - Set the default CPU core frequency as 1GHZ. The following functions are tested on SMD board: - SD/MMC boot, read, write via SDHC1 - eMMC4.4 boot, read, write via SDHC3. - SATA boot, read, write. To support SATA boot via internal clock, please ensure the fuse "SATA_ALT_CLK_REF" was blown. - FEC - UART - clk command - iim command Signed-off-by: Liu Ying <b17645@freescale.com> Signed-off-by: Jason Chen <b02280@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com>
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