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* ENGR00163697 - FEC : Adjust MX53 Network stream throughput.Fugang Duan2011-12-20-0/+110
| | | | | | | | | | | | | | | | | | | | | - When the system is very busy(such as play 1080p streaming in local) the WIFI & FEC performance were very low. - Enable the patch in uboot for WIFI and FEC performance: If WIFI connect to PORT2, enable the config: CONFIG_ADJUST_WIFI_FEC_PERFORMANCE CONFIG_WIFI_SDHC_PORT2 If WIFI connect to port3, enable the config: CONFIG_ADJUST_WIFI_FEC_PERFORMANCE CONFIG_WIFI_SDHC_PORT3 - The solution of the patch: I. Changing M4IF dynamic jump value to zero, which can guarantee FEC the high rate of accessing bus. II. Increase Master 4 priority for FEC. Increase Master 2 and AHBMAX priority for WIFI. - Test result: i.MX53 FEC bandwidth (1080p streaming playback in local): 47.1 Mbits/sec. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00155891 : Fix reboot stress test failed issueRobin Gong2011-11-16-40/+41
| | | | | | | | | | | | | | If we replace DCD mode with plug-in mode in u-boot , we found DDR not stable. We should enable "Force Measurement" after the delay line parameters is configured in the plug-in code, for example: 0x63fd9088 = 0x34333936 0x63fd9090 = 0x49434942 0x63fd90F8 = 0x00000800 "Force Measurement" update all of mx53 DDR script, include mx53_smd,mx53_loco,mx53_evk,mx53_ard, mx53_pcba, at the same time, mx53_pcba will change from DCD mode to plug-in mode in flash_header.S Signed-off-by: Robin Gong <B38343@freescale.com>
* ENGR00157538 remove VDIG_PLL setting in plug-in codeLily Zhang2011-09-23-5/+0
| | | | | | | | According to the datasheet, VDIG_PLL needs to be increased to 1.3v for TO2.0. This operation has been done in the low_level_init.S. Remove the duplicated code here. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00156389: turn off child clocks before reconfigure perclk_rootTerry Lv2011-09-13-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | In addition to ensuring that PERCLK remains at least 2.5 times slower than the AHB clock, certain steps need to be followed to ensure robust operation of PERCLK when reconfiguring the PERCLK clock source. To properly configure the PERCLK clock source, the following steps are required: 1.In the CCGR registers, gate the clocks to all PERCLK-dependent modules. 2.Select the desired input clock for the PERCLK root clock (to be either source from the peripherals main source clock or the lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel bit. 3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers to the desired setting. Refer to the CBCDR register for details. 4.In the CCGR registers, enable the desired clocks for the PERCLK-dependent module clocks. Certain steps are required to reconfigure perclk_root. If don't follow these steps, GPT timer may stop and the kernel stops at " "Calibrating delay loop". Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155283: Set dpgdck0_2_en to 0 when freq is lower than 300MHzTerry Lv2011-09-01-1/+8
| | | | | | | | 1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz. 2. When dpgdck0_2_en is 0, the formula to calculate output freq will be changed to 2 * freq * []. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155739: mx53 evk mmu wrong mapped two csd slotsTerry Lv2011-09-01-10/+4
| | | | | | | mx53 evk mmu wrong mapped two csd slots. Actually evk only has one slot. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00154666-2: Align u-boot mmc command with communityTerry Lv2011-09-01-1/+1
| | | | | | Trivial change to remove build warnings. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00154672: Change to use rom plugins for mx53 boardsTerry Lv2011-08-29-154/+214
| | | | | | | | | | | | | 1. As customer required, we change to use rom plugins for mx53 boards. Tested pass with latest mfg tools. 2. Update DDR3 script based on MX53_TO2_DDR3_LCB_SMD_ARDb_v2.inc. Got from http://compass.freescale.net/livelink/livelink?func=ll &objId=221058910&objAction=browse&viewType=1. 3. Fix a tiny build error in mx53_smd.c. This error will happen when building mx53_smd_mfg. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00144224: MX53: Add MMU mapping for all peripheralsTerry Lv2011-06-09-11/+26
| | | | | | | Not all peripherals are mapped in MMU. Thus we add those missed mapped area. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00143457: Don't let ROM copy .bss sectionJason Liu2011-05-16-2/+3
| | | | | | | | | | | Don't need let ROM copy the .bss section since it will all be zeroed by u-boot at start up, thus it can speed up the boot up time. Need add CONFIG_FLASH_HEADER_OFFSET to the size since ROM will copy from the beginning of the MMC card. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00141363: change mx53 uart clk parent to pll2Jason Chen2011-03-31-13/+20
| | | | | | | | | | Change all mx53 platform uart clk default parent to pll2. MX53 SMD board need support LVDS and HDMI at the same time, they may use the same clock parent-pll4, so kernel need change ipu di clock parent to pll3, after that, uart clock parent need change to pll2 to avoid console mess. Signed-off-by: Jason Chen <b02280@freescale.com>
* ENGR00140982 MX53 Increase VDDGP to 1.25V for 1 GHzAnish Trivedi2011-03-22-2/+2
| | | | | | | | MX53 TO 2.0 requires 1.25V for VDDGP instead of 1.2V in order for the core to operate at 1 GHz. Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00140825: Add mx53 to2.1 chip id recognitionTerry2011-03-20-1/+4
| | | | | | Add mx53 to2.1 chip id recognition. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00138148 MX53 TO2.0 EVK: change the default core as 1GHZLily Zhang2011-01-18-9/+18
| | | | | | | Change the default core frequency as 1GHZ for MX53 TO2.0 EVK board Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137604: Change PLL4 to 455MHz for mx53Terry Lv2011-01-07-1/+6
| | | | | | | Required by display to set ldb. We need to set PLL4 to 455MHz. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137410 MX53 split board files into different foldersLily Zhang2010-12-29-0/+1712
| | | | | | Split different MX53 board files into different folder. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00131705-1 rename mx53_evk folder as mx53_rdLily Zhang2010-09-20-1595/+0
| | | | | | | | Rename the folder "mx53_evk" as "mx53_rd" to put all MX53 board files. Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00131578: Add android recovery mode support for mx53Terry Lv2010-09-20-0/+151
| | | | | | Add android recovery mode support for mx53. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00123924: Reconstructure fuse files and add fuse to mx53.Terry Lv2010-07-16-0/+22
| | | | | | | | | | 1. Reconstructure fuse. Move fuse files to common directory. 2. Read mac from fuse in fec. 3. Remove scc and srk command from fuse command. 4. Change fuse to iim. 5. Add fuse for mx53. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00125045 MX53 Uboot: Adjust VDDGP voltageLily Zhang2010-07-14-3/+3
| | | | | | | 1. Adjust VDDGP voltage for 800MHZ as 1.05v. 2. Correct VDDA comments Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00124984 MX53:Add spi_get_cfg function supportJason Liu2010-07-09-0/+32
| | | | | | | | Add spi_get_cfg function due to the function has been made platform specific and moved out of spi driver. This also fix the build break for mx53 uboot Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00124912 MX53: Fix board ID check issueLily Zhang2010-07-08-1/+1
| | | | | | | | Accoring to board identification table, the ADC data register value range between "0xB9E79F - 0xC00000" indicates 21. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00124710 MX53 Uboot: Add MFG tool supportLily Zhang2010-06-28-0/+7
| | | | | | Add MFG tool support for MX53 EVK Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00124652 UBOOT: MX53 env fails to load when booting from 2nd slotAnish Trivedi2010-06-24-0/+9
| | | | | | Added dynamic check for which sd slot used for boot Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00122651: Add dwc_ahsata supportTerry Lv2010-06-24-2/+9
| | | | | | Add dwc_ahsata support. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00124195 Uboot:Pass EVK RevB board ID to kernelJason Liu2010-06-07-0/+3
| | | | | | | | | Pass EVK RevB board ID to kernel by system_rev[11:8] 2 -->RevB, 1--->ARM2, 0--->RevA, Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00123641 MX53: Add DDR3 CPU board supportJason Liu2010-05-20-3/+59
| | | | | | | | Add DDR3 CPU board support, DDR3 clock 400Mhz Create one config file for it since the DDR3 init script is much different wtih DDR2. Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00123630 Set ddr clk clock according to the board IDrel_imx_2.6.31_10.05.02imx_v2009.08_10.05.02Jason Liu2010-05-19-1/+28
| | | | | | | | | | Set DDR clock to 400Mhz on MX53-EVK with DDR2 1GByte RevB Set DDR clock to 300Mhz on MX53-EVK with DDR2 2GByte RevA1 Remove the clock dump during boot, user can use clk command to get the clock information. Using help clk to get the command help Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00123488 MX53 Board IdentificationJason Liu2010-05-14-3/+167
| | | | | | | | | | | | | | | | The CPU_ID0 analog voltage level is obtained by reading ADC channel 12 of the LTC2495 and the CPU_ID1 analog voltage level is obtained by reading ADC channel 13. The ADC data register value read from the LTC2495 is a 24 bit value. For example, an ADC value that reads between 0xB3CF3E and 0xB9E79E indicates a 130k ohm resistor is populated on the daughtercard, which corresponds to ID level 20 By using CPU_ID0, CPU_ID1 to identify the board for example: CPU_ID0 = 21, CPU_ID1 = 15, MX53-EVK with DDR2 1GByte RevB Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00123278: Support clock operation functionsTerry Lv2010-05-11-1/+1
| | | | | | Support clock operation functions. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00122203 UBOOT: Add MX53 ARM2 board supportJason2010-04-01-34/+110
| | | | | | | | Both EVK and ARM2 board using the same machine id. Currently, use system_rev to diff ARM2 board. DDR freq for ARM2 has been set to 400M, but 300M on EVK. Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00119033: System can not find MMC/SD card in SD slot 1Terry Lv2010-03-30-57/+74
| | | | | | | System can not find MMC/SD card in SD slot 1 when booting from Uboot. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00122046 Update DDR init script for MX53 EVKrel_imx_2.6.31_10.03.00Jason2010-03-26-2/+2
| | | | | | | | | | | | | Update DDR init script according to compass: http://compass.freescale.net/go/216805297 FCP 7 KB 25-Mar-2010 setmem /32 0x53fa8570 = 0x00180000 -> setmem /32 0x53fa8570 = 0x00200000 setmem /32 0x53fa8578 = 0x00180000 -> setmem /32 0x53fa8578 = 0x00200000 Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00121976 UBOOT: some fix for SD/MMC cardJason2010-03-25-6/+43
| | | | | | | | | -Update eSDHC clock setting, -Fix the GPT timer setting, -Fix the boot option pars, -Remove mdelay() function call to improve the performance Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00121774 DDR 300Mhz support for MX53 ubootJason2010-03-19-65/+64
| | | | | | | -update DDR script for 300MHZ support, this script got from Yaniv -increase VDDA to 1.25V Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00121731: Add mmu, l1cache, l2cache support for mx53Terry Lv2010-03-19-0/+74
| | | | | | Add mmu, l1cache, l2cache support for mx53. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00121202 Add uboot support for MX53Jason2010-03-17-0/+914
Add uboot support for MX53 Signed-off-by:Jason Liu <r64343@freescale.com>
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