summaryrefslogtreecommitdiff
path: root/board/freescale/mx53_ard
Commit message (Collapse)AuthorAgeLines
* ENGR00157538 remove VDIG_PLL setting in plug-in codeLily Zhang2011-09-23-5/+0
| | | | | | | | According to the datasheet, VDIG_PLL needs to be increased to 1.3v for TO2.0. This operation has been done in the low_level_init.S. Remove the duplicated code here. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00156389: turn off child clocks before reconfigure perclk_rootTerry Lv2011-09-13-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | In addition to ensuring that PERCLK remains at least 2.5 times slower than the AHB clock, certain steps need to be followed to ensure robust operation of PERCLK when reconfiguring the PERCLK clock source. To properly configure the PERCLK clock source, the following steps are required: 1.In the CCGR registers, gate the clocks to all PERCLK-dependent modules. 2.Select the desired input clock for the PERCLK root clock (to be either source from the peripherals main source clock or the lp_apm clock source). Refer to the CMCBR register, perclk_lp_apm_sel bit. 3.Configure the perclk_pred1, perclk_pred2, and perclk_podf dividers to the desired setting. Refer to the CBCDR register for details. 4.In the CCGR registers, enable the desired clocks for the PERCLK-dependent module clocks. Certain steps are required to reconfigure perclk_root. If don't follow these steps, GPT timer may stop and the kernel stops at " "Calibrating delay loop". Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00139254: Enable MX6Q Uboot Splash ScreenSandor Yu2011-09-02-0/+8
| | | | | | | | | | | | | | Only support LVDS0 splash screen. Enable splash process: 1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2.Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Sandor Yu <r01008@freescale.com>
* ENGR00155283: Set dpgdck0_2_en to 0 when freq is lower than 300MHzTerry Lv2011-09-01-1/+8
| | | | | | | | 1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz. 2. When dpgdck0_2_en is 0, the formula to calculate output freq will be changed to 2 * freq * []. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00154666-2: Align u-boot mmc command with communityTerry Lv2011-09-01-1/+1
| | | | | | Trivial change to remove build warnings. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00154672: Change to use rom plugins for mx53 boardsTerry Lv2011-08-29-152/+274
| | | | | | | | | | | | | 1. As customer required, we change to use rom plugins for mx53 boards. Tested pass with latest mfg tools. 2. Update DDR3 script based on MX53_TO2_DDR3_LCB_SMD_ARDb_v2.inc. Got from http://compass.freescale.net/livelink/livelink?func=ll &objId=221058910&objAction=browse&viewType=1. 3. Fix a tiny build error in mx53_smd.c. This error will happen when building mx53_smd_mfg. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00151695 mx53 ddr3: update ESDREF and MR0Lily Zhang2011-07-21-3/+3
| | | | | | | | | | | Updated mx53 ddr3 script according to MX53_TO2_DDR3_LCB_SMD_ARDb_v1.inc from Michael J Kjar on July 8, 2011: -change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz) -change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from "0x092080b0". This chagned write recovery from 8 clocks to 6 clocks (in line with ESDCFG1[tWR]) Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00144224: MX53: Add MMU mapping for all peripheralsTerry Lv2011-06-09-11/+26
| | | | | | | Not all peripherals are mapped in MMU. Thus we add those missed mapped area. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00143457: Don't let ROM copy .bss sectionJason Liu2011-05-16-1/+2
| | | | | | | | | | | Don't need let ROM copy the .bss section since it will all be zeroed by u-boot at start up, thus it can speed up the boot up time. Need add CONFIG_FLASH_HEADER_OFFSET to the size since ROM will copy from the beginning of the MMC card. Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00143428 mx53 ard RevB: use internal clock for sataLily Zhang2011-05-14-0/+19
| | | | | | Switch to use SATA internal clock in mx53 ARD RevB board. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00141363: change mx53 uart clk parent to pll2Jason Chen2011-03-31-3/+9
| | | | | | | | | | Change all mx53 platform uart clk default parent to pll2. MX53 SMD board need support LVDS and HDMI at the same time, they may use the same clock parent-pll4, so kernel need change ipu di clock parent to pll3, after that, uart clock parent need change to pll2 to avoid console mess. Signed-off-by: Jason Chen <b02280@freescale.com>
* ENGR00140537 mx53: update vddgp according to new data sheetZhou Jingyu2011-03-23-0/+33
| | | | | | mx53: update vddgp according to new data sheet Signed-off-by: Zhou Jingyu <Jingyu.Zhou@freescale.com>
* ENGR00140825: Add mx53 to2.1 chip id recognitionTerry2011-03-20-1/+5
| | | | | | Add mx53 to2.1 chip id recognition. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00140692 Update for DDR3-based MX53 SABRE Auto boardsMahesh Mahadevan2011-03-16-4/+102
| | | | | | | Added a new config file, the DDR setup is similar to the MX53 Quick Start & MX53 SABRE-Tablet ref design boards. Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00138040-3 Protect splashimage related stuffs by configLiu Ying2011-01-17-1/+1
| | | | | | | This patch protects splashimge related stuffs by config option for mx51 bbg, mx53 ard and mx53 smd. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-5 MX53 ARD:Support splashimageLiu Ying2011-01-14-0/+207
| | | | | | | | | | | This patch supports to use pwm wave to control backlight. The pwm rate is 200Hz and the pwm duty is 50%. Use 'lvds_num' env variable to choose to use lvds0 or lvds1. Note that you need to add 'splashimage' env variable to set the memory address of the bmp image. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137791 MX53: Update for MFG toolLily Zhang2011-01-11-8/+1
| | | | | | | | - Add MFG tool support for MX53 SMD and MX53 LOCO boards - Update mx53 ARD MFG defconfig to pass compile Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00137604: Change PLL4 to 455MHz for mx53Terry Lv2011-01-07-1/+6
| | | | | | | Required by display to set ldb. We need to set PLL4 to 455MHz. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137410 MX53 split board files into different foldersLily Zhang2010-12-29-0/+1431
Split different MX53 board files into different folder. Signed-off-by: Lily Zhang <r58066@freescale.com>
generated by cgit v1.1 at 2024-11-19 17:18:45 +0000