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* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* board/freescale/mpc8548cds/mpc8548cds.c: Fix GCC 4.6 build warningKumar Gala2011-11-11-4/+0
| | | | | | | | | | | Fix: mpc8548cds.c: In function 'local_bus_init': mpc8548cds.c:87:7: warning: variable 'lbc_hz' set but not used [-Wunused-but-set-variable] mpc8548cds.c: In function 'lbc_sdram_init': mpc8548cds.c:121:7: warning: variable 'cpu_board_rev' set but not used [-Wunused-but-set-variable] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8548cds: Fix network initializationchenhui zhao2011-11-08-7/+58
| | | | | | | | | Add board_eth_init(). PCIe network card is also supported. Put RGMII init after tsec_eth_init(). Skip initializing eTSEC3 and eTSEC4 with Carrier boards prior to ver 1.3. Signed-off-by: Ebony Zhu Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
* powerpc/mpc8548cds: Code cleanup and refactoringchenhui zhao2011-10-13-4/+4
| | | | | | | | | | | | - Rework tlb and law tables. - PCI2 is not available on MPC8548CDS, so remove it. - Move the memory map to the board config file. - Rewrite the board info according to the manual. - Remove unnecessary macros and redefine some macros to align with other boards. - Fix some typos. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc85xxcds: Fix PCI speedchenhui zhao2011-10-03-2/+2
| | | | | | | | The CDS uses PCICLK as SYSCLK. The PCICLK should be 33333333Hz or 66666666Hz. Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com> Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8548cds: Fix booting messagechenhui zhao2011-10-03-3/+3
| | | | | | Align the output for PCI. Replace "PCI" with "PCI1". Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com>
* powerpc/mpc8548cds: Cleanup mpc8548cds.cZhao Chenhui2011-09-29-7/+0
| | | | | | | Remove unnecessary or dead code/includes. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8548cds: set pci1_hose.config_table after fsl_setup_hoseZhao Chenhui2011-09-09-3/+3
| | | | | | | | The function fsl_setup_hose clears the variable pci1_hose. Set pci1_hose.config_table after it. Signed-off-by: Zhao Chenhui <chenhui.zhao@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Rework MPC8548CDS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-32/+11
| | | | | | | | Remove duplicated code in MPC8548CDS board and utilize the common fsl_pcie_init_board(). We also now dynamically setup the LAWs for PCI controllers based on which PCIe controllers are enabled. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC8xxx DDR: align informational printsBecky Bruce2011-01-14-3/+3
| | | | | | | | | | | | | | | | | | | | Add spaces to cause the informational prints to line up with the ones from init_func_ram() in board.c. Output now looks like this: .... DRAM: Detected 4096 MB of memory This U-Boot only supports < 4G of DDR You could rebuild it with CONFIG_PHYS_64BIT DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC off) .... The prints from lbc_sdram_init() have also been modified to line line up and changed to start with "LBC SDRAM" instead of the confusing "SDRAM". Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: rename sdram_init() lbc_sdram_init()Becky Bruce2011-01-14-2/+1
| | | | | | | | sdram_init() is used to initialize sdram on the lbc. Rename it accordingly. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx boards: initdram() cleanup/bugfixBecky Bruce2011-01-14-38/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences: 1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner. 2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad. The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/8xxx: Replace is_fsl_pci_cfg with is_serdes_configuredKumar Gala2011-01-14-1/+2
| | | | | | | Now that we have serdes support for all 85xx/86xx/Pxxx chips we can replace the is_fsl_pci_cfg() code with the is_serdes_configured(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: Clean up printing of PCI boot infoPeter Tyser2010-11-14-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
* powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliasesKumar Gala2010-07-20-7/+2
| | | | | | | | | | | Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 83xx/85xx/86xx: LBC register cleanupBecky Bruce2010-07-16-9/+4
| | | | | | | | | | | | | | | | | | | | | Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* PCIe, USB: Replace 'end point' references with 'endpoint'Peter Tyser2010-01-17-1/+1
| | | | | | | | | When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
* ppc/85xx: Clean up MPC8548 CDS PCI setup codeKumar Gala2010-01-05-93/+48
| | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc: Remove pci config table pointer relocation fixupsPeter Tyser2009-10-03-7/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc/8xxx: Refactor code to determine if PCI is enabled & agent/hostKumar Gala2009-09-08-3/+3
| | | | | | | | | | | Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode. Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_initKumar Gala2009-08-28-7/+0
| | | | | | | | Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_initKumar Gala2009-08-28-4/+2
| | | | | | | | Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_pci: Move prototypes into fsl_pci.h and remove explicit externsKumar Gala2009-04-04-6/+0
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.hKumar Gala2009-04-04-1/+1
| | | | | | | Rename the pci header for FSL HW so we can move some prototypes in there and stop doing explicit externs Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use common LSDMR defines from asm/fsl_lbc.hKumar Gala2009-03-30-5/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala2009-01-23-2/+2
| | | | | | | Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala2009-01-23-2/+2
| | | | | | | | Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho2008-12-19-1/+1
| | | | | | | | | | | | | | On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* 85xx: Add PORDEVSR_PCI1 definePeter Tyser2008-12-04-1/+1
| | | | | | | | | Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Add CPU 2 errata workaround to all 8548 boardsPeter Tyser2008-12-03-12/+0
| | | | | | | | | | | All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: remove the unused ddr_enable_ecc in the board fileDave Liu2008-12-03-11/+0
| | | | | | | | | | The DDR controller of 8548/8544/8568/8572/8536 processors have the ECC data init feature, and the new DDR code is using the feature, and we don't need the way with DMA to init memory any more. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Coding Style cleanup, update CHANGELOGWolfgang Denk2008-11-02-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-38/+19
| | | | | | | | | | | | Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-41/+41
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* FSL DDR: Convert MPC8548CDS to new DDR code.Jon Loeliger2008-08-27-1/+7
| | | | | Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-12-1/+1
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* 85xx: remove dummy board_early_init_fKumar Gala2008-06-11-5/+0
| | | | | | | A number of board ports have empty version of board_early_init_f for no reason since we control its via CONFIG_BOARD_EARLY_INIT_F. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove unused and unconfigured memory test code.Kumar Gala2008-06-11-39/+0
| | | | | | | Remove unused and unconfigured DDR test code from FSL 85xx boards. Besides, other common code exists. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Limit CPU2 workaround to parts that have the errataAndy Fleming2008-05-07-1/+6
| | | | | Signed-off-by: Ebony Zhu <ebony.zhu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Remove erroneous or extra spd.h #includers.Jon Loeliger2008-03-05-3/+1
| | | | | | | | | | Many of the spd.h #includers don't need it, and wanted to have spd_sdram() declared instead. Since they didn't get that, some also had open coded extern declarations of it instead or as well. Fix it all up by using spd_sdram.h where needed. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Move the MPC8541/MPC8555/MPC8548 CDS board under board/freescale.Kumar Gala2007-12-11-0/+547
Minor path corrections needed to ensure buildability. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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