summaryrefslogtreecommitdiff
path: root/board/freescale/mpc8536ds/mpc8536ds.c
Commit message (Collapse)AuthorAgeLines
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* powerpc/85xx: Add USB device-tree fixup for various platformsramneek mehresh2012-07-06-1/+6
| | | | | | | Add USB device-tree fixup for following platforms: MPC8536DS, P1022DS, P1023RDS, P2020COME, P2020DS, P2041RDB, P3060QDS Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
* powerpc/85xx: don't display address map size (32-bit vs. 36-bit) during bootTimur Tabi2012-04-24-6/+1
| | | | | | | | | | | | | | | | Most 85xx boards can be built as a 32-bit or a 36-bit. Current code sometimes displays which of these is actually built, but it's inconsistent. This is especially problematic since the "default" build for a given 85xx board can be either one, so if you don't see a message, you can't always know which size is being used. Not only that, but each board includes code that displays the message, so there is duplication. The 'bdinfo' command has been updated to display this information, so we don't need to display it at boot time. The board-specific code is deleted. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc8536ds: Invert SDHC_WP pin polarityXie Xiaobo2011-10-09-0/+8
| | | | | | | | | | | | | MPC8536 Rev 1.0 silicon have NMG_eSDHC118 erratum, so that the SDHC write protected pin polarity does not follow the SD card standard in MPC8536 Rev 1.0 silicon. The MPC8536DS board invert the SDHC_WP pin as a workaround. However, this silicon erratum has been fixed in Rev 1.1, So need invert the SDHC_WP polarity again when use the MPC8536 Rev1.1 and greater on MPC8536DS board. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/mpc8536ds: Add eSPI support for MPC8536DSXie Xiaobo2011-10-09-4/+2
| | | | | | | | | | 1. The SD_DATA[4:7] signals are shared with the SPI chip selects on 8536DS, so don't set MPC85xx_PMUXCR_SD_DATA that config eSDHC data bus-width to 4-bit and enable SPI signals. 2. Add eSPI controller and SPI-FLASH definition. Signed-off-by: Xie Xiaobo <r63061@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* tsec: Convert tsec to use PHY LibAndy Fleming2011-04-20-0/+6
| | | | | | | | | | | | | This converts tsec to use the new PHY Lib. All of the old PHY support is ripped out. The old MDIO driver is split off, and placed in fsl_mdio.c. The initialization is modified to initialize the MDIO driver as well. The powerpc config file is modified to configure PHYLIB if TSEC_ENET is configured. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
* powerpc/85xx: Rework MPC8536DS pci_init_board to use common FSL PCIe codeKumar Gala2011-01-14-102/+14
| | | | | | | Remove duplicated code in MPC8536DS board and utilize the common fsl_pcie_init_board(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx boards: initdram() cleanup/bugfixBecky Bruce2011-01-14-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've noticed, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences: 1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner. 2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad. The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Tested-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Cleanup SGMII detection and reportingKumar Gala2011-01-14-18/+9
| | | | | | | | Use new is_serdes_configured to determine if TSECs are in SGMII mode and report that on the various boards that use or can be configured in SGMII mode in board_eth_init() instead of in the PCI init code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Fix SERDES/eTSEC message indentationPeter Tyser2010-11-14-4/+4
| | | | | | | | | | | | | Previously some mpc85xx boards printed indented messages such as the following on bootup: printf(" eTSEC4 is in sgmii mode.\n"); printf(" Serdes2 disalbed\n"); The bootup appearance looks cleaner if the indentation is removed which aligns these messages with other bootup output. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: galak@kernel.crashing.org
* fsl: Clean up printing of PCI boot infoPeter Tyser2010-11-14-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously boards used a variety of indentations, newline styles, and colon styles for the PCI information that is printed on bootup. This patch unifies the style to look like: ... NAND: 1024 MiB PCIE1: connected as Root Complex Scanning PCI bus 01 04 01 8086 1010 0200 00 04 01 8086 1010 0200 00 03 00 10b5 8112 0604 00 02 01 10b5 8518 0604 00 02 02 10b5 8518 0604 00 08 00 1957 0040 0b20 00 07 00 10b5 8518 0604 00 09 00 10b5 8112 0604 00 07 01 10b5 8518 0604 00 07 02 10b5 8518 0604 00 06 00 10b5 8518 0604 00 02 03 10b5 8518 0604 00 01 00 10b5 8518 0604 00 PCIE1: Bus 00 - 0b PCIE2: connected as Root Complex Scanning PCI bus 0d 0d 00 1957 0040 0b20 00 PCIE2: Bus 0c - 0d In: serial ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> CC: wd@denx.de CC: sr@denx.de CC: galak@kernel.crashing.org
* powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliasesKumar Gala2010-07-20-20/+2
| | | | | | | | | | | Previously we used an alias the pci node to determine which node to fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to find the node to update. Additionally, we replace the code in each board with a single macro call that makes assumes uniform naming and reduces duplication in this area. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Convert MPC8536DS to using board common ICS307 codeKumar Gala2010-07-16-148/+0
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/fsl-sata: Use is_serdes_configured() to determine if SATA is enabledKumar Gala2010-05-12-11/+0
| | | | | | | | | | | | On the MPC85xx platform if we have SATA its connected on SERDES. Determing if SATA is enabled via sata_initialize should not be board specific and thus we move it out of the MPC8536DS board code. Additionally, now that we have is_serdes_configured() we can determine if the given SATA port is enabled and error out if its not in the driver. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/mpc8536ds: Use is_serdes_configured() to determine of PCIe enabledKumar Gala2010-05-12-4/+29
| | | | | | | | | | | | The new is_serdes_configured covers a broader range of devices than the PCI specific code. Use it instead as we convert away from the is_fsl_pci_cfg() code. Additionally move to setting LAWs for PCI based on if its configured. Also updated PCI FDT fixup code to remove PCI controllers from dtb if they are configured. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: improve the PIXIS code and fix a few bugsTimur Tabi2010-04-07-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx boards. This makes the code easier to read and more flexible. Delete pixis.h, because none of the exported functions were actually being used by any other file. Make all of the functions in pixis.c 'static'. Remove "#include pixis.h" from every file that has it. Remove some unnecessary #includes. Make 'pixis_base' into a macro, so that we don't need to define it in every function. Add "while(1);" loops at the end of functions that reset the board, so that execution doesn't continue while the reset is in progress. Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where appropriate. Replace ulong/uint with their spelled-out equivalents. Remove unnecessary typecasts, changing the types of some variables if necessary. Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make it easier for specific boards to support variations in the PIXIS registers sets. No current boards appears to need this feature. Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD. Apparently, "pixis_reset altbank" has never worked on this board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* PCIe, USB: Replace 'end point' references with 'endpoint'Peter Tyser2010-01-17-3/+3
| | | | | | | | | When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
* ppc/85xx: Make flash TLB entry determined at runtime on FSL boardsKumar Gala2010-01-05-1/+1
| | | | | | | Rather than hard coding which TLB entry the FLASH is mapped with we can use find_tlb_idx to determine the entry. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Clean up MPC8536 DS PCI setup codeMingkai Hu2010-01-05-191/+66
| | | | | | | | Use new fsl_pci_init_port() that reduces amount of duplicated code in the board ports, use IO accessors and clean up printing of status info. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Refactor code to determine if PCI is enabled & agent/hostKumar Gala2009-09-08-8/+7
| | | | | | | | | | | Refactor the code into a simple bitmask lookup table that determines if a given PCI controller is enabled and if its in host/root-complex or agent/end-point mode. Each processor in the PQ3/MPC86xx family specified different encodings for the cfg_host_agt[] and cfg_IO_ports[] boot strapping signals. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Cleanup whitespace in mpc8536ds.cKumar Gala2009-08-28-11/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold fsl_pci_setup_inbound_windows into fsl_pci_initKumar Gala2009-08-28-12/+0
| | | | | | | | Every platform that calls fsl_pci_init calls fsl_pci_setup_inbound_windows before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* pci/fsl_pci_init: Fold pci_setup_indirect into fsl_pci_initKumar Gala2009-08-28-9/+4
| | | | | | | | Every platform that calls fsl_pci_init calls pci_setup_indirect before it calls fsl_pci_init. There isn't any reason to just call it from fsl_pci_init and simplify things a bit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/86xx: Replace in8/out8 with in_8/out_8 on FSL boardsKumar Gala2009-07-22-8/+14
| | | | | | | The pixis code used in8/out8 all over the place. Replace it with in_8/out_8 macros. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Report which "bank" of NOR flash we are booting from on FSL boardsKumar Gala2009-07-22-4/+35
| | | | | | | | | | | | | | The p2020DS, MPC8536DS, MPC8572DS, MPC8544DS boards are capable of swizzling the upper address bits of the NOR flash we boot out of which creates the concept of "virtual" banks. This is useful in that we can flash a test of image of u-boot and reset to one of the virtual banks while still maintaining a working image in "bank 0". The PIXIS FPGA exposes registers on LBC which we can use to determine which "bank" we are booting out of (as well as setting which bank to boot out of). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_pci: Move prototypes into fsl_pci.h and remove explicit externsKumar Gala2009-04-04-6/+0
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_pci: Renamed immap_fsl_pci.h to fsl_pci.hKumar Gala2009-04-04-1/+1
| | | | | | | Rename the pci header for FSL HW so we can move some prototypes in there and stop doing explicit externs Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add eSDHC support for 8536 DSAndy Fleming2009-02-16-0/+14
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* Fixup SGMII PHY ids in the device treeAndy Fleming2009-02-16-0/+5
| | | | | | | | | | | The device tree's PHY addresses need to be fixed up if we're using the SGMII Riser Card. The 8572, 8536, and 8544 DS boards were modified to call this function. Code idea taken from Liu Yu <yu.liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* mpc8536ds.c: include sata.h to for needed function prototypesWolfgang Denk2009-01-28-0/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* SATA: do not auto-initialize during bootMike Frysinger2009-01-27-3/+3
| | | | | | | | | | | | Rather than have the board code initialize SATA automatically during boot, make the user manually run "sata init". This brings the SATA subsystem in line with common U-Boot policy. Rather than having a dedicated weak function "is_sata_supported", people can override sata_initialize() to do their weird board stuff. Then they can call the actual __sata_initialize(). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala2009-01-23-4/+4
| | | | | | | Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala2009-01-23-10/+10
| | | | | | | | Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: separate FLASH BASE virtual from physical addressKumar Gala2009-01-23-1/+1
| | | | | | | | | | Added a CONFIG_SYS_FLASH_BASE_PHYS for use as the physical address and maintain CONFIG_SYS_FLASH_BASE as the virtual address of the flash. This allows us to deal with 36-bit phys on these boards in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: the DDR tlb is missed for the !CONFIG_SPD_EEPROM caseDave Liu2008-12-03-4/+2
| | | | | | | we need TLB entry for DDR at !SPD case. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: remove the unused ddr_enable_ecc in the board fileDave Liu2008-12-03-10/+0
| | | | | | | | | | The DDR controller of 8548/8544/8568/8572/8536 processors have the ECC data init feature, and the new DDR code is using the feature, and we don't need the way with DMA to init memory any more. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Coding Style cleanup, update CHANGELOGWolfgang Denk2008-11-02-3/+3
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Convert all fsl_pci_init users to new APIsKumar Gala2008-10-24-73/+37
| | | | | | | | | | | | Converted ATUM8548, MPC8536DS, MPC8544DS, MPC8548CDS, MPC8568MDS, MPC8572DS, TQM85xx, and SBC8548 to use fsl_pci_setup_inbound_windows() and ft_fsl_pci_setup(). With these changes the board code is a bit smaller and we get dma-ranges set in the device tree for these boards. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andrew Fleming-AFLEMING <afleming@freescale.com>
* 85xx: Fix compile warning in mpc8536ds.cKumar Gala2008-10-21-1/+0
| | | | | | | mpc8536ds.c: In function 'is_sata_supported': mpc8536ds.c:615: warning: unused variable 'devdisr' Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Enabled the Freescale SGMII riser card on 8536DSJason Jin2008-10-18-0/+42
| | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* 85xx: Improve flash remapping on MPC8572DS & MPC8536DSKumar Gala2008-10-18-6/+4
| | | | | | | | Changing the flash from cacheable to cache-inhibited was taking a significant amount of time due to the fact that we were iterating over the full 256M of flash. Instead we can just flush the L1 d-cache and invalidate the i-cache. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-72/+72
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Fix compiler warning in lib_ppc/board.cHeiko Schocher2008-10-15-1/+1
| | | | | | | Fix compiler warning introduced by commit 0f8cbc18 Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Do not init SATA when disabled on 8536DS.Jason Jin2008-10-14-0/+12
| | | | | | | | | | SGMII and SATA share the serdes on MPC8536 CPU, When SATA disabled and the driver still try to access the SATA registers, the cpu will hangup. This patch try to fix this by reading the serdes status before the SATA initialize. Signed-off-by: Jason Jin <Jason.jin@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* mpc85xx: Add support for the MPC8536DS reference boardKumar Gala2008-08-27-0/+653
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-11-01 16:25:45 +0000