| Commit message (Collapse) | Author | Age | Lines | |
|---|---|---|---|---|
| * | armv7: LS1021a: enable i-cache in start.S | Xiaoliang Yang | 2016-10-06 | -0/+6 |
| | | | | | | | | | | | Delete CONFIG_SKIP_LOWLEVEL_INIT define in ls1021atwr.h and ls1021aqds.h can let it run cpu_init_cp15 to enable i-cache. First stage of u-boot can run faster after that. There is a description about skip lowlevel init in board/freescale/ls1021atwr/README. Signed-off-by: Xiaoliang Yang <xiaoliang.yang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> | |||
| * | arm: ls102xa: Add basic support for LS1021ATWR board | Wang Huan | 2014-09-08 | -0/+109 |
| LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021ATWR board. One DDR controller DUART1 is used as the console For the detail board information, please refer to README. Signed-off-by: Chen Lu <chen.lu@freescale.com> Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> | ||||
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index : arm-boot/u-boot-imx.git | |
| U-boot NXP imx6 | git@iatec.biz |
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