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* powerpc/QorIQ: fix network frame manager TBI PHY address settingsRoy Zang2011-11-08-8/+0
| | | | | | | | | | | | TBI PHY address (TBIPA) register has been set in general frame manager phy init funciton dtsec_init_phy() in drivers/net/fm/eth.c So remove the duplicate code on QorIQ frame manager Ethernet related platforms, which include Hydra board, P4080DS board and P2041rdb board. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Cc: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpersShengzhou Liu2011-10-18-22/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add common function fdt_set_node_status() to assist in various locations that we set a nodes status. This function utilizes the status values that are part of the EPAPR spec (on power.org). fdt_set_status_by_alias() is based on fdt_set_node_status() but uses an alias string to identify the node to update. We also add some shortcut functions to help the common cases of setting "okay" and "disabled": fdt_status_okay() fdt_status_disabled() fdt_status_okay_by_alias() fdt_status_disabled_by_alias() Finally, we fixup the corenet_ds ethernet code which previously had a function by the same name that can be replaced with the new helpers. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
* powerpc/hydra: Add ethernet support on P5020/P3041 DS boardsTimur Tabi2011-09-29-0/+553
Add support for RGMII, SGMII, and XAUI (10Gb) Ethernet on P3041DS & P5020DS ("Hydra"). The lane_to_slot[] array is initialized dynamically, since board switches can be used to control the muxing of SERDES lanes to slots. The BRDCFG1 PIXIS register is used to route the MII bus to the appropriate slot. The SERDES configuration is queried to help determine the routing between MACs and slot/phy combination. If a XAUI card is inserted, muxing for that card is enabled and never turned off. The PHY address for the 10G XAUI card depends on the slot in which it's inserted. If it's in slot 1, the address is 4. If it's in slot 2, the address is 0. Update the MDIO routing in the P3041DS and P5020DS device trees based on the board-level muxing. The SERDES configuration determines which SGMII/XGMII boards are located in which slots, and so the MDIO bus needs to be muxed correctly whenever talking to a PHY connected to any Fman MAC. The Fman Ethernet nodes in the device tree also need to be routed to the correct PHYs. Removed CONFIG_SYS_FMAN_FW as its not used anywhere. Signed-off-by: Ioana Radulescu <ruxandra.radulescu@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>