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| * freescale/qixis: Add support for booting from SD/QSPIGong Qianyu2016-01-25-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1.Use "qixis_reset sd" to boot from SD 2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support 3.Use "qixis_reset qspi" to boot from QSPI flash On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be pin-multiplexed. So the switches are different between SD boot with IFC support and SD boot with QSPI support. The default booting from SD is with IFC support. Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | powerpc/board/t4240rdb: Enable VID supportYing Zhang2016-01-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | board/freescale/common: Check IR chip mode for VID supportYing Zhang2016-01-25-1/+20
|/ | | | | | | | | IR chip on all the boards are required to be used in Intel mode to support VID. VDD will not be adjusted if IR chip is used in other modes. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* block: pass block dev not num to read/write/erase()Stephen Warren2016-01-13-1/+1
| | | | | | | | | | | This will allow the implementation to make use of data in the block_dev structure beyond the base device number. This will be useful so that eMMC block devices can encompass the HW partition ID rather than treating this out-of-band. Equally, the existence of the priv field is crying out for this patch to exist. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* pfuze: Fix unsigned variable for less-than-zero comparisonYe.Li2016-01-07-1/+2
| | | | | | | | | | | | According to the Coverity result, a unsigned int variable is used fo less- than-zero comparison, the result is never true. Need to fix the variable type to signed int. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal2015-12-15-12/+22
| | | | | | | | | | LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* freescale: fman: make sure phy-handle property is big endianShaohui Xie2015-12-13-0/+2
| | | | | | | | | | When creating phy-handle property, an unsigned int value is created by fdt_create_phandle, and memcpy is used to get the value, since DTS is big endian, the value cannot be used directly on little endian SoCs, it should be converted by cpu_to_fdt32. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043aqds: add LS1043AQDS board supportShaohui Xie2015-11-30-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043AQDS Specification: ------------------------- Memory subsystem: * 2GByte DDR4 DIMM * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two RGMII ports * XFI 10G port * SGMII * QSGMII with 4x 1G ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> [York Sun: Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
* mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter CardYangbo Lu2015-11-02-0/+3
| | | | | | | | | When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card), enable EVDD automatic control via SDHC_VS. This could support SD card IO voltage switching for UHS-1 speed mode. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter CardYangbo Lu2015-11-02-0/+2
| | | | | | | | If adapter card type identification is supported for platform, we would enable dat[4:7] for eMMC4.5 Adapter Card. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls1021atwr: optimize the deep sleep latencytang yuantian2015-10-30-4/+0
| | | | | | | | | | | | It will take more than 1s when wake up from deep sleep. Most of the time is spent on outputing information. This patch reduced the deep sleep latency by: 1. avoid outputing system informaton 2. remove flush cache after DDR restore 3. skip reloading second stage uboot binary when SD boot Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* SECURE_BOOT: Correct reading of ITS bitAneesh Bansal2015-10-30-1/+1
| | | | | | | | | The ITS bit was being read incorrectly beacause of operator precedence. The same ahs been corrected. Signed-off-by: Lawish Deshmukh <lawish.deshmukh@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043a: Add Fman supportShaohui Xie2015-10-29-1/+5
| | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/ls1021a: move ns_access to common fileMingkai Hu2015-10-29-2/+8
| | | | | | | | | | Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Pointers in ESBC header made 32 bitAneesh Bansal2015-10-29-10/+10
| | | | | | | | | | For the Chain of Trust, the esbc_validate command supports 32 bit fields for location of the image. In the header structure definition, these were declared as pointers which made them 64 bit on a 64 bit core. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl: common: pfuze: no use original pfuze code if DM_PMICPeng Fan2015-08-12-0/+2
| | | | | | | | | | | | If enable DM PMIC and REGULATOR, we should not use original power framework. So need to comment out the pfuze code for original power framework, when CONFIG_DM_PMIC_PFUZE100 defined. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041Aneesh Bansal2015-07-31-0/+15
| | | | | | | | | | | | | | | | | | | Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/fsl/common: Fix eeprom system version endiannessJaiprakash Singh2015-07-20-4/+4
| | | | | | | | | | | | SYSTEM ID EPPROM always store SYSTEM version info in big endian format. SoC with ARM or PowerPC core should read/write version info from eeprom in BIG endian format. So use cpu-specific APIs to read SYSTEM version. Signed-off-by: Jaiprakash Singh <b44839 at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* pmic: pfuze100 fix typoPeng Fan2015-05-19-2/+2
| | | | | | Change PUZE_100_SW1ABCONF to PFUZE100_SW1ABCONF Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka2015-05-13-1/+1
| | | | | | | | | | | | | | CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian <Yuantian.Tang@freescale.com> CC: York Sun <yorksun@freescale.com> CC: Steve Rae <srae@broadcom.com> CC: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: fsl_esdhc: Add adapter card type identification supportYangbo Lu2015-05-04-0/+14
| | | | | | | | | | | | Add adapter card type identification support by reading FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function, define CONFIG_FSL_ESDHC_ADAPTER_IDENT. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> [York Sun: resolve conflicts in README.fsl-esdhc] Reviewed-by: York Sun <yorksun@freescale.com>
* fsl/deepsleep: avoid the DDR restore from being optimized outTang Yuantian2015-05-04-4/+4
| | | | | | | | | | | Function dp_ddr_restore is to restore the first 128-byte space of DDR. However those codes may be optimized out by compiler since the destination address is at 0x0. In order to avoid compiler optimization, we restore the space from high address, which is not at 0x0, to low address. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-04-28-2/+1
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| * iMX: Fix compilation error when enabling SECURE_BOOTgaurav rana2015-04-22-2/+1
| | | | | | | | | | | | | | | | | | Move the compilation of file fsl_validate.c in MACRO CONFIG_CMD_ESBC_VALIDATE. This file should be compiled only when the above MACRO is defined This caused a break in compilation of iMX platforms when compiling for SECURE_BOOT Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com>
* | freescale/qixis: Add support for booting from NANDScott Wood2015-04-23-10/+21
| | | | | | | | | | | | | | Use "qixis_reset nand" to reset the board to boot from NAND. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* | QE/DeepSleep: add QE deepsleep support for armZhao Qiang2015-04-21-0/+6
| | | | | | | | | | | | | | | | Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | QE/DeepSleep: add QE deepsleep support for mpc85xxZhao Qiang2015-04-21-0/+8
| | | | | | | | | | | | | | | | Muram will power off during deepsleep, and the microcode of qe in muram will be lost, it should be reload when resume. Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Add bootscript support to esbc_validate.gaurav rana2015-04-21-0/+16
|/ | | | | | | | | | | | | | | | | | | | | | | | 1. Default environment will be used for secure boot flow which can't be edited or saved. 2. Command for secure boot is predefined in the default environment which will run on autoboot (and autoboot is the only option allowed in case of secure boot) and it looks like this: #define CONFIG_SECBOOT \ "setenv bs_hdraddr 0xe8e00000;" \ "esbc_validate $bs_hdraddr;" \ "source $img_addr;" \ "esbc_halt;" #endif 3. Boot Script can contain esbc_validate commands and bootm command. Uboot source command used in default secure boot command will run the bootscript. 4. Command esbc_halt added to ensure either bootm executes after validation of images or core should just spin. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-03-05-0/+880
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| * SECURE_BOOT : enable esbc_validate command for powerpc and arm platforms.gaurav rana2015-03-05-0/+6
| | | | | | | | | | | | | | | | | | | | esbc_validate command uses various IP Blocks: Security Monitor, CAAM block and SFP registers. Hence the respective CONFIG's are enabled. Apart from these CONFIG_SHA_PROG_HW_ACCEL and CONFIG_RSA are also enabled. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * SECURE BOOT: Add command for validation of imagesgaurav rana2015-03-05-0/+874
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. esbc_validate command is meant for validating header and signature of images (Boot Script and ESBC uboot client). SHA-256 and RSA operations are performed using SEC block in HW. This command works on both PBL based and Non PBL based Freescale platforms. Command usage: esbc_validate img_hdr_addr [pub_key_hash] 2. ESBC uboot client can be linux. Additionally, rootfs and device tree blob can also be signed. 3. In the event of header or signature failure in validation, ITS and ITF bits determine further course of action. 4. In case of soft failure, appropriate error is dumped on console. 5. In case of hard failure, SoC is issued RESET REQUEST after dumping error on the console. 6. KEY REVOCATION Feature: QorIQ platforms like B4/T4 have support of srk key table and key revocation in ISBC code in Silicon. The srk key table allows the user to have a key table with multiple keys and revoke any key in case of particular key gets compromised. In case the ISBC code uses the key revocation and srk key table to verify the u-boot code, the subsequent chain of trust should also use the same. 6. ISBC KEY EXTENSION Feature: This feature allows large number of keys to be used for esbc validation of images. A set of public keys is being signed and validated by ISBC which can be further used for esbc validation of images. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-03-02-0/+15
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| * arm: ls1021x: Add support for initializing CAAM's stream idAlison Wang2015-02-24-0/+15
| | | | | | | | | | | | | | | | | | There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id for using the same SMMU3 on LS1021A. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-02-13-1/+1
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| * powerpc: mpc83xx: remove MPC8360ERDK, EMPC8360EMDS supportMasahiro Yamada2015-01-23-1/+1
| | | | | | | | | | | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Dave Liu <daveliu@freescale.com> Cc: Anton Vorontsov <avorontsov@ru.mvista.com>
* | pmic:pfuze implement pmic_mode_initPeng Fan2015-02-11-0/+39
|/ | | | | | | | | | | | | | | | | | | | This patch is to implement pmic_mode_init function, and add prototype in header file. This function is to set switching mode for pmic buck regulators to improve system efficiency. Mode: OFF: The regulator is switched off and the output voltage is discharged. PFM: In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency. PWM: In this mode, the regulator is always in PWM mode operation regardless of load conditions. APS: In this mode, the regulator moves automatically between pulse skipping mode and PWM mode depending on load conditions. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com>
* ARM: ls102xa: Setting device's stream id for SMMUs.Xiubo Li2014-12-11-0/+20
| | | | | | | | | | | | LS1 has 4 SMMUs for address translation of the masters. All the SMMUs' stream IDs are 8-bit. The address translation depends on the stream ID of the incoming transaction. Each master has unique stream ID assigned to it and is configurable through SCFG registers. The stream ID for the masters is identical and share the same register field of STREAM ID registers. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ARM: ls102xa: allow all the peripheral access permission as R/W.Xiubo Li2014-12-11-0/+32
| | | | | | | | | | | | | | | The Central Security Unit (CSU) allows secure world software to change the default access control policies of peripherals/bus slaves, determining which bus masters may access them. This allows peripherals to be separated into distinct security domains. Combined with SMMU configuration of the system masters privileges, these features provide protection against indirect unauthorized access to data. For now we configure all the peripheral access permissions as R/W. Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl/sleep: updated the deep sleep framework for QorIQ platformsTang Yuantian2014-12-11-0/+210
| | | | | | | | | | | | | With the introducing of generic board and ARM-based cores, current deep sleep framework doesn't work anymore. This patch will convert the current framework to adapt this change. Basically it does: 1. Converts all the Freescale's DDR driver to support deep sleep. 2. Added basic framework support for ARM-based and PPC-based cores separately. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* ls102xa: qixis: Add CONFIG_QIXIS_I2C_ACCESS macroAlison Wang2014-12-11-0/+7
| | | | | | | | | | | Through adding CONFIG_QIXIS_I2C_ACCESS macro, QIXIS_READ(reg)/QIXIS_WRITE(reg, value) can be used for both i2c and ifc access to QIXIS FPGA. This is more convenient for coding. Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/b4860qds: add workaround for XFIShaohui Xie2014-12-05-0/+112
| | | | | | | | | | | | | | | XFI does not work stable on current board, it's due to heat sink issue, to make it work stable the board needs additional heat sink, enable two XFI lanes only. Right now we do not have such an erratum for the issue, so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it. The workaround will only be used in XFI protocols and only if the hwconfig indicates that XFI is prefered. A new VSC3308 config function is used instead of re-use the original function, to avoid making the function complex and ugly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t208xqds: VID supportYing Zhang2014-12-05-0/+512
| | | | | | | | | | | | The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-11-26-2/+2
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| * arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR boardAlison Wang2014-11-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SystemID information could be read through I2C1 from EEPROM on LS1021ATWR board. As LS1 is a little-endian processor, getting the version ID by be32_to_cpu() is wrong. Fix it by using e.version directly. This change will be compatible for both ARM and PowerPC. As there is an errata that I2C1 could not work in SD boot, reading EEPROM through I2C1 is disabled too in SD boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge git://git.denx.de/u-boot-fdtTom Rini2014-11-26-2/+3
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| * | fdt: Allow ft_board_setup() to report failureSimon Glass2014-11-21-2/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-24-0/+67
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| * | imx: mx6sabre common: Factorize the Pfuze init functionYe.Li2014-11-20-0/+67
| |/ | | | | | | | | | | | | | | | | Since the Pfuze initializations are similar on various mx6 SABRE boards. Factorize the initialization to a common function in file board/freescale/common/pfuze.c. So that all SABRE boards BSP can share the function. Signed-off-by: Ye.Li <B37916@freescale.com>
* | linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-3/+3
|/ | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* cosmetic: replace MIN, MAX with min, maxMasahiro Yamada2014-09-24-1/+1
| | | | | | | The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
generated by cgit v1.1 at 2024-11-07 19:36:08 +0000