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* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-26-19/+86
|\ | | | | | | | | | | | | trini: Drop local memset() from examples/standalone/mem_to_mem_idma2intr.c Signed-off-by: Tom Rini <trini@konsulko.com>
| * armv8: ls1046aqds: Add LS1046AQDS board supportShaohui Xie2016-09-14-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1046AQDS Specification: ------------------------- Memory subsystem: * 8GByte DDR4 SDRAM (64bit bus) * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 64 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two XFI 10G ports * Two SGMII ports * Two RGMII ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * nxp: ls102xa: add LS1 PSCI system suspendHongbo Zhang2016-09-14-1/+34
| | | | | | | | | | | | | | | | The deep sleep function of LS1 platform, is mapped into PSCI system suspend function, this patch adds implementation of it. Signed-off-by: Hongbo Zhang <hongbo.zhang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set R/W permission to PCIeHou Zhiqiang2016-09-14-0/+28
| | | | | | | | | | Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * fsl: csu: add an API to set individual device access permissionHou Zhiqiang2016-09-14-14/+20
| | | | | | | | | | | | | | | | Add this API to make the individual device is able to be set to the specified permission. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | arch, board: squash lines for immediate returnMasahiro Yamada2016-09-23-3/+1
|/ | | | | | | | Remove unneeded variables and assignments. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Minkyu Kang <mk7.kang@samsung.com> Reviewed-by: Angelo Dureghello <angelo@sysam.it>
* SECURE_BOOT: Enable chain of trust in SPL frameworkSumit Garg2016-07-26-1/+33
| | | | | | | | | | | Override jump_to_image_no_args function to include validation of u-boot image using spl_validate_uboot before jumping to u-boot image. Also define macros in SPL framework to enable crypto operations. Reviewed-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-0/+56
| | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* board: freescale: common: Add flag for LBMAP brdcfg reg offsetAbhimanyu Saini2016-06-03-2/+9
| | | | | | | | | | | Add QIXIS_LBMAP_BRDCFG_REG to the save offset of LBMAP configuration register instead of hardcoding it in set_lbmap() function. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board: freescale: common: Conditionally compile IFC QXIS funcAbhimanyu Saini2016-06-03-0/+2
| | | | | | | | | | Check if qixis supports memory-mapped read/write before compiling IFC based qixis read/write functions. Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* board: ls102xa: Fix ICID setupVincent Siles2016-06-03-2/+5
| | | | | | | LS102A ref manual dictates that ICID have to be written to the MSB of the ICID register, not to the LSB. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com>
* arm: uniform usage of u32 in ls102x caam configVincent Siles2016-05-18-1/+1
| | | | | | | Mix usage of uint32_t and u32 fixed in favor of u32. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
* arm: Fix SCFG ICID reg addressesVincent Siles2016-05-18-2/+2
| | | | | | | | | | | | | On the LS102x boards, in order to initialize the ICID values of masters, the dev_stream_id array holds absolute offsets from the base of SCFG. In ls102xa_config_ssmu_stream_id, the base pointer is cast to uint32_t * before adding the offset, leading to an invalid address. Casting it to void * solves the issue. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Fix various typos, scattered over the code.Robert P. J. Day2016-05-05-2/+2
| | | | | | | | | | | | | Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
* armv8/ls2080ardb: Enable VID supportRai Harninder2016-03-29-1/+14
| | | | | | | | This patch enable VID support for ls2080ardb platform. It uses the common VID driver. Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* SECURE BOOT: Change fsl_secboot_validate func to pass image addrSaksham Jain2016-03-29-12/+26
| | | | | | | | | Use a pointer to pass image address to fsl_secboot_validate(), instead of using environmental variable "img_addr". Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* SECURE BOOT: Halt execution when secure boot failSaksham Jain2016-03-29-1/+6
| | | | | | | | | | | | In case of fatal failure during secure boot execution (e.g. header not found), reset is asserted to stop execution. If the RESET_REQ is not tied to HRESET, this allows the execution to continue. Add esbh_halt() after the reset to make sure execution stops. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* armv8: fsl-lsch3: Add new header for secure bootSaksham Jain2016-03-29-5/+30
| | | | | | | | | | | | | | For secure boot, a header is used to identify key table, signature and image address. A new header structure is added for lsch3. Currently key extension (IE) feature is not supported. Single key feature is not supported. Keys must be in table format. Hence, SRK (key table) must be present. Max key number has increase from 4 to 8. The 8th key is irrevocable. A new barker Code is used. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* freescale: vid: Return i2c mux to default channelWenbin Song2016-03-21-3/+9
| | | | | | | | IR chip is on one of the channels on multiplexed I2C-bus. Reset to default channel after accessing. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* qe: move drivers/qe/qe.h to include/fsl_qe.hQianyu Gong2016-02-24-2/+2
| | | | | | | | As the QE firmware struct is shared with Fman, move the header file out of drivers/qe/. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-01-27-142/+316
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| * secure_boot: change error handler for esbc_validateAneesh Bansal2016-01-27-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | In case of error while executing esbc_validate command, SNVS transition and issue of reset is required only for secure-boot. If boot mode is non-secure, this is not required. Similarly, esbc_halt command which puts the core in Spin Loop is applicable only for Secure Boot. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * secure_boot: enable chain of trust for ARM platformsAneesh Bansal2016-01-27-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Chain of Trust is enabled for ARM platforms (LS1021 and LS1043). In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * secure_boot: create function to determine boot modeAneesh Bansal2016-01-27-0/+53
| | | | | | | | | | | | | | | | | | A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * SECURE BOOT: support for validation of dynamic imageAneesh Bansal2016-01-25-16/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some images to be validated are relocated to a dynamic address at run time. So, these addresses cannot be known befor hand while signing the images and creating the header offline. So, support is required to pass the image address to the validate function as an argument. If an address is provided to the function, the address field in Header is not read and is treated as a reserved field. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * SECURE BOOT: separate function created for signatureAneesh Bansal2016-01-25-44/+54
| | | | | | | | | | | | | | | | | | | | | | The code for image hash calculation, hash calculation from RSA signature and comparison of hashes has been mobed to a separate function. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * SECURE BOOT: separate functions for reading keysAneesh Bansal2016-01-25-73/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | Separate functions are created for reading and checking the sanity of Public keys: - read_validate_single_key - read_validate_ie_tbl - read_validate_srk_table Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * SECURE BOOT: change prototype of fsl_secboot_validate functionAneesh Bansal2016-01-25-12/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The prototype and defination of function fsl_secboot_validate has been changed to support calling this function from another function within u-boot. Only two aruments needed: 1) header address - Mandatory 2) SHA256 string - optional Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * freescale/qixis: Add support for booting from SD/QSPIGong Qianyu2016-01-25-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1.Use "qixis_reset sd" to boot from SD 2.Use "qixis_reset sd_qspi" to boot from SD with QSPI support 3.Use "qixis_reset qspi" to boot from QSPI flash On some SoCs such as LS1021A and LS1043A, IFC and QSPI could be pin-multiplexed. So the switches are different between SD boot with IFC support and SD boot with QSPI support. The default booting from SD is with IFC support. Once QSPI is enabled(IFC disabled), only use I2C to access QIXIS. Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | powerpc/board/t4240rdb: Enable VID supportYing Zhang2016-01-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | board/freescale/common: Check IR chip mode for VID supportYing Zhang2016-01-25-1/+20
|/ | | | | | | | | IR chip on all the boards are required to be used in Intel mode to support VID. VDD will not be adjusted if IR chip is used in other modes. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* block: pass block dev not num to read/write/erase()Stephen Warren2016-01-13-1/+1
| | | | | | | | | | | This will allow the implementation to make use of data in the block_dev structure beyond the base device number. This will be useful so that eMMC block devices can encompass the HW partition ID rather than treating this out-of-band. Equally, the existence of the priv field is crying out for this patch to exist. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* pfuze: Fix unsigned variable for less-than-zero comparisonYe.Li2016-01-07-1/+2
| | | | | | | | | | | | According to the Coverity result, a unsigned int variable is used fo less- than-zero comparison, the result is never true. Need to fix the variable type to signed int. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
* armv8/ls1043ardb: add SECURE BOOT target for NORAneesh Bansal2015-12-15-12/+22
| | | | | | | | | | LS1043ARDB Secure Boot Target from NOR has been added. - Configs defined to enable esbc_validate. - ESBC Address in header is made 64 bit. - SMMU is re-configured in Bypass mode. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* freescale: fman: make sure phy-handle property is big endianShaohui Xie2015-12-13-0/+2
| | | | | | | | | | When creating phy-handle property, an unsigned int value is created by fdt_create_phandle, and memcpy is used to get the value, since DTS is big endian, the value cannot be used directly on little endian SoCs, it should be converted by cpu_to_fdt32. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043aqds: add LS1043AQDS board supportShaohui Xie2015-11-30-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1043AQDS Specification: ------------------------- Memory subsystem: * 2GByte DDR4 DIMM * 128 Mbyte NOR flash single-chip memory * 512 Mbyte NAND flash * 16 Mbyte high-speed SPI flash * SD connector to interface with the SD memory card Ethernet: * Two RGMII ports * XFI 10G port * SGMII * QSGMII with 4x 1G ports PCIe: supports Gen 1 and Gen 2 SATA 3.0: one SATA 3.0 port USB 3.0: two micro AB connector and one type A connector UART: supports two UARTs up to 115200 bps for console Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> [York Sun: Add CONFIG_SYS_NS16550=y in defconfig] Reviewed-by: York Sun <yorksun@freescale.com>
* mmc: fsl_esdhc: enable EVDD automatic control for SD/MMC Legacy Adapter CardYangbo Lu2015-11-02-0/+3
| | | | | | | | | When detecting SDHC Adapter Card Type 2(SD/MMC Legacy Adapter Card), enable EVDD automatic control via SDHC_VS. This could support SD card IO voltage switching for UHS-1 speed mode. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* mmc: fsl_esdhc: enable dat[4:7] for eMMC4.5 Adapter CardYangbo Lu2015-11-02-0/+2
| | | | | | | | If adapter card type identification is supported for platform, we would enable dat[4:7] for eMMC4.5 Adapter Card. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* arm: ls1021atwr: optimize the deep sleep latencytang yuantian2015-10-30-4/+0
| | | | | | | | | | | | It will take more than 1s when wake up from deep sleep. Most of the time is spent on outputing information. This patch reduced the deep sleep latency by: 1. avoid outputing system informaton 2. remove flush cache after DDR restore 3. skip reloading second stage uboot binary when SD boot Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* SECURE_BOOT: Correct reading of ITS bitAneesh Bansal2015-10-30-1/+1
| | | | | | | | | The ITS bit was being read incorrectly beacause of operator precedence. The same ahs been corrected. Signed-off-by: Lawish Deshmukh <lawish.deshmukh@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/ls1043a: Add Fman supportShaohui Xie2015-10-29-1/+5
| | | | | | | | Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/ls1021a: move ns_access to common fileMingkai Hu2015-10-29-2/+8
| | | | | | | | | | Config Security Level Register is different between different SoCs, so put the CSL register definition into the arch specific directory. Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Pointers in ESBC header made 32 bitAneesh Bansal2015-10-29-10/+10
| | | | | | | | | | For the Chain of Trust, the esbc_validate command supports 32 bit fields for location of the image. In the header structure definition, these were declared as pointers which made them 64 bit on a 64 bit core. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* fsl: common: pfuze: no use original pfuze code if DM_PMICPeng Fan2015-08-12-0/+2
| | | | | | | | | | | | If enable DM PMIC and REGULATOR, we should not use original power framework. So need to comment out the pfuze code for original power framework, when CONFIG_DM_PMIC_PFUZE100 defined. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041Aneesh Bansal2015-07-31-0/+15
| | | | | | | | | | | | | | | | | | | Secure Boot Target is added for NAND for P3041. For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In case of secure boot, this default address maps to Boot ROM. The Boot ROM code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. In case of NAND Secure Boot, CONFIG_SYS_RAMBOOT is enabled and CPC is configured as SRAM. U-Boot binary will be located on SRAM configured at address 0xBFF00000. In the U-Boot code, TLB entries are created to map the virtual address 0xFFF00000 to physical address 0xBFF00000 of CPC configured as SRAM. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/fsl/common: Fix eeprom system version endiannessJaiprakash Singh2015-07-20-4/+4
| | | | | | | | | | | | SYSTEM ID EPPROM always store SYSTEM version info in big endian format. SoC with ARM or PowerPC core should read/write version info from eeprom in BIG endian format. So use cpu-specific APIs to read SYSTEM version. Signed-off-by: Jaiprakash Singh <b44839 at freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar at freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* pmic: pfuze100 fix typoPeng Fan2015-05-19-2/+2
| | | | | | Change PUZE_100_SW1ABCONF to PFUZE100_SW1ABCONF Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka2015-05-13-1/+1
| | | | | | | | | | | | | | CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian <Yuantian.Tang@freescale.com> CC: York Sun <yorksun@freescale.com> CC: Steve Rae <srae@broadcom.com> CC: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mmc: fsl_esdhc: Add adapter card type identification supportYangbo Lu2015-05-04-0/+14
| | | | | | | | | | | | Add adapter card type identification support by reading FPGA STAT_PRES1 register SDHC Card ID[0:2] bits. To use this function, define CONFIG_FSL_ESDHC_ADAPTER_IDENT. Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> [York Sun: resolve conflicts in README.fsl-esdhc] Reviewed-by: York Sun <yorksun@freescale.com>
* fsl/deepsleep: avoid the DDR restore from being optimized outTang Yuantian2015-05-04-4/+4
| | | | | | | | | | | Function dp_ddr_restore is to restore the first 128-byte space of DDR. However those codes may be optimized out by compiler since the destination address is at 0x0. In order to avoid compiler optimization, we restore the space from high address, which is not at 0x0, to low address. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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