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* powerpc/b4860qds: add workaround for XFIShaohui Xie2014-12-05-0/+112
| | | | | | | | | | | | | | | XFI does not work stable on current board, it's due to heat sink issue, to make it work stable the board needs additional heat sink, enable two XFI lanes only. Right now we do not have such an erratum for the issue, so use a define CONFIG_SYS_FSL_B4860QDS_XFI_ERR to identify it. The workaround will only be used in XFI protocols and only if the hwconfig indicates that XFI is prefered. A new VSC3308 config function is used instead of re-use the original function, to avoid making the function complex and ugly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/t208xqds: VID supportYing Zhang2014-12-05-0/+512
| | | | | | | | | | | | The fuse status register provides the values from on-chip voltage ID efuses programmed at the factory. These values define the voltage requirements for the chip. u-boot reads FUSESR and translates the values into the appropriate commands to set the voltage output value of an external voltage regulator. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-11-26-2/+2
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| * arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR boardAlison Wang2014-11-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SystemID information could be read through I2C1 from EEPROM on LS1021ATWR board. As LS1 is a little-endian processor, getting the version ID by be32_to_cpu() is wrong. Fix it by using e.version directly. This change will be compatible for both ARM and PowerPC. As there is an errata that I2C1 could not work in SD boot, reading EEPROM through I2C1 is disabled too in SD boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | Merge git://git.denx.de/u-boot-fdtTom Rini2014-11-26-2/+3
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| * | fdt: Allow ft_board_setup() to report failureSimon Glass2014-11-21-2/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-24-0/+67
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| * | imx: mx6sabre common: Factorize the Pfuze init functionYe.Li2014-11-20-0/+67
| |/ | | | | | | | | | | | | | | | | Since the Pfuze initializations are similar on various mx6 SABRE boards. Factorize the initialization to a common function in file board/freescale/common/pfuze.c. So that all SABRE boards BSP can share the function. Signed-off-by: Ye.Li <B37916@freescale.com>
* | linux/kernel.h: sync min, max, min3, max3 macros with LinuxMasahiro Yamada2014-11-23-3/+3
|/ | | | | | | | | | | | | | | | | | | | U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
* cosmetic: replace MIN, MAX with min, maxMasahiro Yamada2014-09-24-1/+1
| | | | | | | The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* video: dcu: Add Sii9022A HDMI Transmitter supportWang Huan2014-09-08-0/+168
| | | | | | | | On LS1021ATWR, Silicon's Sii9022A HDMI Transmitter is used. This patch adds the common setting for this chip. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* fsl/diu: ch7301 encoder split off from t1040qds/diu.cWang Dongsheng2014-08-12-0/+151
| | | | | | | | The ch7301 encoder not only used in t1040qds platform, so we split it for t1042rdb and LSx platform. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* board/freescale: Move CRC32 offset in NXID v1 data formatEbony Zhu2014-05-16-3/+4
| | | | | | | | | | According to AN3638, CRC of NXID v1 is at the end of the 256-byte I2C memory. The wrong CRC32 offset prevents Uboot from reading system information from EEPROM. No NXID v0 is being used on Freescale boards. Signed-off-by: Ebony Zhu <b45385@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* powerpc/freescale: Change the return value of mac_read_from_eeprom()York Sun2014-05-13-3/+3
| | | | | | | | | | | The return value has not been checked by its caller, until recent change of using generic board architecture. The error of this function is not critical enough to hang the system. Printing the warning message is enough to catch user's attention. U-boot should continue to boot to give user a chance to fix the EEPROM. Chaning the return value to 0 to avoid hanging in the board_init_r(). Signed-off-by: York Sun <yorksun@freescale.com>
* board/freescale/common: ZM7300 driverShaveta Leekha2014-05-13-0/+258
| | | | | | | | | | | Adds Support for PowerOne ZM7300 voltage regulator. This device is available on some Freescale Boards like B4860QDS and has to be programmed to adjust the voltage on the board. The device is accessible via I2C interface. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
* kbuild: add dummy obj-y to create built-in.oMasahiro Yamada2014-02-19-1/+4
| | | | | | | | | We are going to switch over to Kbuild in upcoming commits. Each makefile must have non-empty obj- or obj-y to generate built-in.o on Kbuild. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* eSDHC: Calculate envaddr accroding to the address formatHaijun.Zhang2014-01-22-0/+29
| | | | | | | | | | | | | | | | | On BSC9131, BSC9132, P1010 : For High Capacity SD Cards (> 2 GBytes), the 32-bit source address specifies the memory address in block address format. Block length is fixed to 512 bytes as per the SD High Capacity specification. So we need to convert the block address format to byte address format to calculate the envaddr. If there is no enough space for environment variables or envaddr is larger than 4GiB, we relocate the envaddr to 0x400. The address relocated is in the front of the first partition that is assigned for sdboot only. Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com> Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Makefile: delete unnecessary CPPFLAGS settingsMasahiro Yamada2013-12-13-2/+0
| | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* board: powerpc: convert makefiles to Kbuild styleMasahiro Yamada2013-11-01-64/+33
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de>
* powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROMShengzhou Liu2013-10-16-0/+4
| | | | | | | | | | | | Some boards use System EEPROM with 128-bytes instead of 256-bytes. Since we regard 256-bytes EEPROM as standard EEPROM with default value for MAX_NUM_PORTS. For those non-256-bytes EEPROM, we can redefine MAX_NUM_PORTS in board-specific file to override the default MAX_NUM_PORTS. This patch doesn't impact on previous existing boards. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
* powerpc/t1040qds: Add T1040QDS boardPrabhakar Kushwaha2013-10-16-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1040QDS is a high-performance computing evaluation, development and test platform supporting the T1040 QorIQ Power Architecture™ processor. T1040QDS board Overview ----------------------- - Four e5500 cores, each with a private 256 KB L2 cache - 256 KB shared L3 CoreNet platform cache (CPC) - Interconnect CoreNet platform - 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support - Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions: - Packet parsing, classification, and distribution - Queue management for scheduling, packet sequencing, and congestion management - Cryptography Acceleration - RegEx Pattern Matching Acceleration - IEEE Std 1588 support - Hardware buffer management for buffer allocation and deallocation - Ethernet interfaces - Integrated 8-port Gigabit Ethernet switch - Four 1 Gbps Ethernet controllers - SERDES Connections, 8 lanes supporting: — PCI Express: supporting Gen 1 and Gen 2; — SGMII — QSGMII — SATA 2.0 — Aurora debug with dedicated connectors - DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and Interleaving -IFC/Local Bus - NAND flash: 8-bit, async, up to 2GB. - NOR: 8-bit or 16-bit, non-multiplexed, up to 512MB - GASIC: Simple (minimal) target within Qixis FPGA - PromJET rapid memory download support - Ethernet - Two on-board RGMII 10/100/1G ethernet ports. - PHY #0 remains powered up during deep-sleep - QIXIS System Logic FPGA - Clocks - System and DDR clock (SYSCLK, “DDRCLK”) - SERDES clocks - Power Supplies - Video - DIU supports video at up to 1280x1024x32bpp - USB - Supports two USB 2.0 ports with integrated PHYs — Two type A ports with 5V@1.5A per port. — Second port can be converted to OTG mini-AB - SDHC - SDHC port connects directly to an adapter card slot, featuring: - Supporting SD slots for: SD, SDHC (1x, 4x, 8x) and/or MMC — Supporting eMMC memory devices - SPI - On-board support of 3 different devices and sizes - Other IO - Two Serial ports - ProfiBus port - Four I2C ports Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> [York Sun: fix conflict in boards.cfg] Acked-by-by: York Sun <yorksun@freescale.com>
* Coding Style cleanup: remove trailing white spaceWolfgang Denk2013-10-14-5/+5
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* powerpc/common/vsc3316: remove const from vsc3316_config parameter defineShaohui Xie2013-08-20-2/+2
| | | | | | | | | Since the parameters need to be modified according to different Serdes protocols at runtime, the const will block this. Also remove const from arrays define used by vsc3316_config. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc: p1022ds: Enable P1022DS to boot from SD Card with SPLYing Zhang2013-08-20-2/+0
| | | | | | | Enable p1022ds to start from eSDHC with SPL. Signed-off-by: Ying Zhang <b40530@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/mpc85xx: Cleanup license header in source filesYork Sun2013-08-12-28/+2
| | | | | | | | | | | | Fix the license header introduced by the following patches Add TWR-P10xx board support Add T4240EMU target IDT8T49N222A configuration code Add C29x SoC support Add support for C29XPCIE board Signed-off-by: York Sun <yorksun@freescale.com>
* board/freescale/common: IDT8T49N222A configuration codeShaveta Leekha2013-08-09-0/+341
| | | | | | | | | | | | | Add code for configuring IDT8T49N222A device for various output refclks - The IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer with alarm and monitoring functions suitable for networking and communications applications. It is able to generate wide range of output frequencies. - In B4860QDS, it has been used to generate different refclks to SerDes modules - Programming of these devices are performed by I2C interface. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* powerpc/mpc8xxx: Add memory reset controlYork Sun2013-08-09-0/+20
| | | | | | | | | JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-351/+24
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* powerpc/pixis: Fix pixis help messageYork Sun2013-06-20-0/+2
| | | | | | | | "pixis_reset help" command prints the message without a new line "\n", which makes the prompt on the same line. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: new SPL support for IFC NANDPrabhakar Kushwaha2013-06-20-0/+10
| | | | | | | | | | | | | | Linker script is not able find start.o binary. So add its absolute path in u-boot-spl.lds. This change is similar to u-boot-nand.lds common/Makefile: Avoid compiling unnecssary files fsl_ifc_spl.c : It is is responsible for reading u-boot binary from NAND flash and copying into DDR. It also transfer control from NAND SPL to u-boot image present in DDR. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/qixis: add clock measurement registersEd Swarthout2013-05-24-1/+5
| | | | | | | | | | | | | QIXIS includes frequency measurement functions for each major processor clock input. After reset (and after clocks are stable), QIXIS measures the clocks against a reference frequency and stores the results in CLK_FREQ registers. A base register supplies a multiplier which allows directly obtaining the measured value, without requiring knowledge of the target system or QIXIS core frequency. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/p1022ds: Add support for NAND and NAND boot using SPLMatthew McClintock2013-05-02-0/+6
| | | | | | | | | | | | | | Add defines needed to access NAND, remove second flash bank that is actually connected to NAND. Add nand booting support for P1022DS with hardcoded DDR config using SPL framework from 2011 Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com> Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/freescale/common/cds_pci_ft.c: Fix rotate wrong cells in interrupt-map ↵Jiang Bin2013-05-02-3/+23
| | | | | | | | | | | | property For linux 3.x, the size of each item in interrupt-map property is 9 not 7. Don't use the static value and calculate the size with following cells: PCI #address-cells, PCI #interrupt-cells, PIC address, PIC #address-cells, PIC #interrupt-cells. Signed-off-by: Bin Jiang <bin.jiang@windriver.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* env_mmc: add support for redundant environmentMichael Heimpold2013-05-01-1/+1
| | | | | | | | This patch add support for storing the environment redundant on mmc devices. Substantially it re-uses the logic from the NAND implementation, that means using an incremental counter for marking newer data. Signed-off-by: Michael Heimpold <mhei@heimpold.de>
* board/common: Add support for QIXIS read/write using i2cPrabhakar Kushwaha2013-01-30-0/+23
| | | | | | | | | | | | QIXIS FPGA is accessable via both i2c and flash controller. Only flash controller access is supported. Add support of i2c based access. It is quite useful in the scenario where either flash controller path is broken or not present. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/qixis: enable qixis dump command and add switch dumping commandShaveta Leekha2013-01-30-12/+36
| | | | | | | | | | | | | Remove #ifdef so that "qixis dump" command is always available Add "qixis_reset switch" command to dump switch settings Qixis doesn't have 1:1 switch mapping. We need to reverse engineer from registers to figure out switch settings. Not all bits are available. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/freescale/common:Add support of QTAG registerPrabhakar Kushwaha2013-01-30-0/+49
| | | | | | | | | | | | | QIXIS FPGA's QIXIS Tag Access register (QTAG) defines TAG, VER, DATE, IMAGE fields. These fields have FPGA build version, image name and build date information. Add support to parse these fields to have complete FPGA image information. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: add support for the Freescale P5040DS Superhydra reference boardTimur Tabi2012-11-27-1/+3
| | | | | | | | | The P5040DS reference board (a.k.a "Superhydra") is an enhanced version of P3041DS/P5020DS ("Hydra") reference board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/mpc85xx: sparse fixesKim Phillips2012-11-04-4/+8
| | | | | | | | | | | | | | | | | fsl_corenet_serdes.c:485:6: warning: symbol '__soc_serdes_init' was not declared. Should it be static? cpu_init.c:185:6: warning: symbol 'invalidate_cpc' was not declared. Should it be static? bcsr.c:28:27: warning: non-ANSI function declaration of function 'enable_8568mds_duart' bcsr.c:39:33: warning: non-ANSI function declaration of function 'enable_8568mds_flash_write' bcsr.c:46:34: warning: non-ANSI function declaration of function 'disable_8568mds_flash_write' bcsr.c:53:29: warning: non-ANSI function declaration of function 'enable_8568mds_qe_mdio' bcsr.c:28:33: warning: non-ANSI function declaration of function 'enable_8569mds_flash_write' bcsr.c:33:34: warning: non-ANSI function declaration of function 'disable_8569mds_flash_write' bcsr.c:38:28: warning: non-ANSI function declaration of function 'enable_8569mds_qe_uec' bcsr.c:63:47: warning: non-ANSI function declaration of function 'disable_8569mds_brd_eeprom_write_protect' ngpixis.c:245:1: error: directive in argument list ngpixis.c:247:1: error: directive in argument list Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* board/freescale/common: VSC3316/VSC3308 initialization codeShaveta Leekha2012-10-22-0/+219
| | | | | | | | | | | | | | Add code for configuring VSC3316/3308 crosspoint switches Add README to understand the APIs - VSC 3316/3308 is a low-power, low-cost asynchronous crosspoint switch capable of data rates upto 11.5Gbps. VSC3316 has 16 input and 16 output ports whereas VSC3308 has 8 input and 8 output ports. Programming of these devices are performed by two-wire or four-wire serial interface. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/board: add present2 register definition for QIXISShengzhou Liu2012-10-22-2/+2
| | | | | | | | According to new QIXIS system definition, update QIXIS registers set to add present2 register instead of obsolete ctl_sys2. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* board/freescale/common:QIXIS:Fix magic number usagePrabhakar Kushwaha2012-10-22-12/+7
| | | | | | | | | | | | QIXIS FPGA layout defines the address of registers but The actual register bit implementation is board-specific, So avoid use of magic numbers as it may vary across different boards's QIXIS FPGA implementation. Also, Avoid board specific defines in common/qixis.h Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: remove support for the Freescale P3060Timur Tabi2012-08-23-2/+0
| | | | | | | | The P3060 was cancelled before it went into production, so there's no point in supporting it. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: introduce function serdes_device_from_fm_port()Timur Tabi2012-08-23-0/+33
| | | | | | | | | In order to figure out which SerDes lane a given Fman port is connected to, we need a function that maps the fm_port namespace to the srds_prtcl namespace. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: Slave module for boot from PCIELiu Gang2012-08-23-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When boot from PCIE, slave's core should be in holdoff after powered on for some specific requirements. Master will release the slave's core at the right time by PCIE interface. Slave's ucode and ENV can be stored in master's memory space, then slave can fetch them through PCIE interface. For the corenet platform, ucode is for Fman. NOTE: Because the slave can not erase, write master's NOR flash by PCIE interface, so it can not modify the ENV parameters stored in master's NOR flash using "saveenv" or other commands. environment and requirement: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image is in master NOR flash. 3. Put the slave's ucode and ENV into it's own memory space. 4. Normally boot from local NOR flash. 5. Configure PCIE system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to one PCIE interface by RCW. 3. RCW should configure the SerDes, PCIE interfaces correctly. 4. Must set all the cores in holdoff by RCW. 5. Must be powered on before master's boot. For the slave module, need to finish these processes: 1. Set the boot location to one PCIE interface by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID of one PCIE for the boot. 4. Set a specific TLB entry in order to fetch ucode and ENV from master. 5. Set a LAW entry with the TargetID one of the PCIE ports for ucode and ENV. 6. Slave's u-boot image should be generated specifically by make xxxx_SRIO_PCIE_BOOT_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. In addition, the processes are very similar between boot from SRIO and boot from PCIE. Some configurations like the address spaces can be set to the same. So the module of boot from PCIE was added based on the existing module of boot from SRIO, and the following changes were needed: 1. Updated the README.srio-boot-corenet to add descriptions about boot from PCIE, and change the name to README.srio-pcie-boot-corenet. 2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to "xxxx_SRIO_PCIE_BOOT", and the image builded with "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and from PCIE. 3. Updated other macros and documents if needed to add information about boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macroLiu Gang2012-08-23-13/+0
| | | | | | | | | | | | | | | | When compile the slave image for boot from SRIO, no longer need to specify which SRIO port it will boot from. The code will get this information from RCW and then finishes corresponding configurations. This has the following advantages: 1. No longer need to rebuild an image when change the SRIO port for boot from SRIO, just rewrite the new RCW with selected port, then the code will get the port information by reading new RCW. 2. It will be easier to support other boot location options, for example, boot from PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/sgmii: To support PHY link state auto detect in SGMII modeHongtao Jia2012-08-08-8/+49
| | | | | | | | | | | | | | | PHYs on SGMII riser card are used in SGMII mode with different external IRQs from eTSEC. This means in SGMII mode phy-handle and phy-connection-type under ethernet node should be updated. Otherwise the PHY interrupt can not be handled therefor PHY link state change can not be auto detected. For we have seperate SGMII PHY nodes, ethernet PHY reg fixup is not needed but it's still be kept to guarantee the sgmii mode could work with old device tree. Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Jia Hongtao <B38951@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: fdt_set_phy_handle() should return an error codeTimur Tabi2012-07-06-18/+20
| | | | | | | fdt_set_phy_handle() makes several FDT calls that could fail, so it should not be hiding these errors. Signed-off-by: Timur Tabi <timur@freescale.com>
* powerpc/corenet_ds: Slave uploads ucode when boot from SRIOLiu Gang2012-04-24-0/+14
| | | | | | | | | | | | | | | | | When boot from SRIO, slave's ucode can be stored in master's memory space, then slave can fetch the ucode image through SRIO interface. For the corenet platform, ucode is for Fman. Master needs to: 1. Put the slave's ucode image into it's own memory space. 2. Set an inbound SRIO window covered slave's ucode stored in master's memory space. Slave needs to: 1. Set a specific TLB entry in order to fetch ucode from master. 2. Set a LAW entry with the TargetID SRIO1 or SRIO2 for ucode. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
* powerpc/corenet_ds: Slave module for boot from SRIOLiu Gang2012-04-24-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the powerpc processors with SRIO interface, boot location can be configured from SRIO1 or SRIO2 by RCW. The processor booting from SRIO can do without flash for u-boot image. The image can be fetched from another processor's memory space by SRIO link connected between them. The processor boots from SRIO is slave, the processor boots from normal flash memory space and can help slave to boot from its memory space is master. They are different environments and requirements: master: 1. NOR flash for its own u-boot image, ucode and ENV space. 2. Slave's u-boot image in master NOR flash. 3. Normally boot from local NOR flash. 4. Configure SRIO switch system if needed. slave: 1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV. 2. Boot location should be set to SRIO1 or SRIO2 by RCW. 3. RCW should configure the SerDes, SRIO interfaces correctly. 4. Slave must be powered on after master's boot. 5. Must define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE because of no ucode locally. For the slave module, need to finish these processes: 1. Set the boot location to SRIO1 or SRIO2 by RCW. 2. Set a specific TLB entry for the boot process. 3. Set a LAW entry with the TargetID SRIO1 or SRIO2 for the boot. 4. Slave's u-boot image should be generated specifically by make xxxx_SRIOBOOT_SLAVE_config. This will set SYS_TEXT_BASE=0xFFF80000 and other configurations. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
generated by cgit v1.1 at 2024-11-09 16:16:44 +0000