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* Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.stroese2003-04-04-1/+7
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* Make compile clean, fix the usual small problems.wdenk2003-03-26-1/+0
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* esd PCI405 updated.stroese2003-03-26-0/+32
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* esd PCI405 updated.stroese2003-03-25-782/+1015
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* CPCI4052 update (support for revision 3).stroese2003-03-20-816/+888
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* Add "pcidelay" environment variable (in ms, enabled via CONFIG_PCI_BOOTDELAY).stroese2003-02-14-1/+1
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* Initial revisionwdenk2002-11-03-0/+953
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* Initial revisionwdenk2002-11-03-0/+475
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* Initial revisionwdenk2002-11-03-0/+1405
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* Initial revisionwdenk2002-09-20-0/+738
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* Initial revisionwdenk2002-09-18-0/+774
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* Initial revisionwdenk2002-08-30-0/+586
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* Initial revisionwdenk2002-08-26-0/+448
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* Initial revisionwdenk2002-08-17-0/+1612
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* Initial revisionwdenk2002-08-14-0/+156
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* Initial revisionwdenk2002-08-06-0/+240
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* Initial revisionwdenk2002-07-20-0/+426
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* Initial revisionwdenk2002-07-18-0/+32
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* Initial revisionwdenk2002-07-07-0/+138
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* Initial revisionwdenk2002-06-07-0/+772
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* Initial revisionwdenk2002-05-15-0/+342
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* Initial revisionwdenk2002-04-01-0/+92
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* Initial revisionwdenk2002-03-02-0/+703
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* Initial revisionwdenk2001-12-28-0/+478
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* Initial revisionwdenk2001-11-26-0/+4818
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* Initial revisionwdenk2001-10-15-0/+29
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* Initial revisionwdenk2001-10-07-0/+103
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* Initial revisionwdenk2001-08-05-0/+2192
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* Initial revisionwdenk2001-07-19-0/+205