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* Changed CPCI405 to use CTS instead of DSR on PPC405 UART1.stroese2003-04-04-1/+7
* Make compile clean, fix the usual small problems.wdenk2003-03-26-1/+0
* esd PCI405 updated.stroese2003-03-26-0/+32
* esd PCI405 updated.stroese2003-03-25-782/+1015
* CPCI4052 update (support for revision 3).stroese2003-03-20-816/+888
* Add "pcidelay" environment variable (in ms, enabled via CONFIG_PCI_BOOTDELAY).stroese2003-02-14-1/+1
* Initial revisionwdenk2002-11-03-0/+953
* Initial revisionwdenk2002-11-03-0/+475
* Initial revisionwdenk2002-11-03-0/+1405
* Initial revisionwdenk2002-09-20-0/+738
* Initial revisionwdenk2002-09-18-0/+774
* Initial revisionwdenk2002-08-30-0/+586
* Initial revisionwdenk2002-08-26-0/+448
* Initial revisionwdenk2002-08-17-0/+1612
* Initial revisionwdenk2002-08-14-0/+156
* Initial revisionwdenk2002-08-06-0/+240
* Initial revisionwdenk2002-07-20-0/+426
* Initial revisionwdenk2002-07-18-0/+32
* Initial revisionwdenk2002-07-07-0/+138
* Initial revisionwdenk2002-06-07-0/+772
* Initial revisionwdenk2002-05-15-0/+342
* Initial revisionwdenk2002-04-01-0/+92
* Initial revisionwdenk2002-03-02-0/+703
* Initial revisionwdenk2001-12-28-0/+478
* Initial revisionwdenk2001-11-26-0/+4818
* Initial revisionwdenk2001-10-15-0/+29
* Initial revisionwdenk2001-10-07-0/+103
* Initial revisionwdenk2001-08-05-0/+2192
* Initial revisionwdenk2001-07-19-0/+205
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