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* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-24-34/+2
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* x86: Add FDT SPI node for linkSimon Glass2013-03-19-0/+11
| | | | | | Add a memory-mapped 8GB SPI chip. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Adjust link device tree include fileSimon Glass2013-03-04-1/+1
| | | | | | | | This is currently set to coreboot.dtsi, but we cannot support this on old device tree compilers (dtc <= 1.3), so adjust to use ARCH_CPU_DTS to let the Makefile preprocessor sort this out. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: fdt: Create basic .dtsi file for corebootSimon Glass2012-12-06-12/+30
| | | | | | | | This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Add a minimal device tree for alex x86Gabe Black2012-11-30-0/+30
| | | | | | | | | | The device tree now includes the necessary console configuration information. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Remove coreboot start16 codeSimon Glass2012-11-30-34/+0
| | | | | | This file is no longer needed for coreboot. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Remove coreboot start16 codeSimon Glass2012-11-28-13/+0
| | | | | | | Now that coreboot doesn't need the start16 code, remove it. We need to remove the CONFIG_SYS_X86_RESET_VECTOR option from coreboot.h also. Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: coreboot: Modify u-boot code to allow building coreboot payloadVadim Bendebury2012-11-28-0/+37
| | | | | | | | | This prevents the preprocessor from complaining when processing variadic macros Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Graeme Russ <graeme.russ@gmail.com>
* x86: coreboot: Move non-board specific files to coreboot arch directoryStefan Reinauer2012-11-28-119/+0
| | | | | | | | | | coreboot.c and coreboot_pci.c don't contain board specific but only coreboot specific code. Hence move it to the coreboot directory in arch/x86/cpu (which should probably be moved out of cpu/ in another commit) Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Import code from coreboot's libpayload to parse the coreboot tableGabe Black2011-12-19-0/+10
| | | | | | | | | | | | | This change also forces the lib_sysinfo structure to be in the .data section. Otherwise it ends up in the .bss section. U-boot assumes that it doesn't need to copy it over during relocation, and instead fills that whole section with zeroes. If we really were booting from ROM that would be appropriate, but we need some information from the coreboot tables (memory size) before then and have to fill that structure before relocation. We skirt u-boot's assumption by putting this in .data where it assumes there is still read only but non-zero data. Signed-off-by: Gabe Black <gabeblack@chromium.org>
* x86: Initial commit for running as a coreboot payloadGabe Black2011-12-19-0/+235
Add a target for running u-boot as a coreboot payload in boards.cfg, a board, CPU and a config. This is a skeleton implementation which always reports the size of memory as 64 MB. Signed-off-by: Gabe Black <gabeblack@chromium.org>
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