| Commit message (Collapse) | Author | Age | Lines |
|
|
|
|
|
|
| |
For all practical u-boot purposes, TSECs don't differ throughout the
mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
|
|
|
|
|
|
|
|
|
|
| |
* Cleaned up the CDS PCI Config Tables and added NULL entries to
the end
* Fixed PCIe LAWBAR assignemt to use the cpu-relative address
* Fixed 85xx PCI code to assign powar region sizes based on the
config values (rather than hard-coding them)
* Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
| |
The other pagesz constants use one letter to specify order of
magnitude. Also change the one reference to it in mpc8548cds/init.S
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|
|
|
|
|
|
| |
Fix the 85xxcds tsec bug.
When enable PCI, tsec.o should be added to u-boot.lds to make tsec work.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
|
|
|
|
|
| |
This patch apply workaround of CPU2 errata on MPC8548CDS board.
Signed-off-by:Ebony Zhu <ebony.zhu@freescale.com>
|
|
|
|
|
|
| |
Enable PCI function and add PEX & rapidio memory map on MPC8548CDS
board.
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
|
|
|
|
| |
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
|
|
|
| |
Signed-off-by: Matthew McClintock <msm@freescale.com>
|
|\ |
|
| |
| |
| |
| | |
Based on patch by Mike Frysinger, 20 Jun 2006
|
| | |
|
|\ \
| | |
| | |
| | |
| | |
| | | |
Conflicts:
drivers/tsec.c
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
* Added support for using eTSEC 3 and eTSEC 4 on the 8548 CDS.
This will only work on rev 1.3 boards (but doesn't break older boards)
* Cleaned up some comments to reflect the expanded role of tsec
in other systems
|
| | |
| | |
| | |
| | | |
* Added code to swizzle the IRQ map for the PCI
|
|\ \ \
| |/ /
|/| /
| |/
| |
| | |
Conflicts:
board/stxxtc/Makefile
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Modifications are based on the linux kernel approach and
support two use cases:
1) Add O= to the make command line
'make O=/tmp/build all'
2) Set environement variable BUILD_DIR to point to the desired location
'export BUILD_DIR=/tmp/build'
'make'
The second approach can also be used with a MAKEALL script
'export BUILD_DIR=/tmp/build'
'./MAKEALL'
Command line 'O=' setting overrides BUILD_DIR environent variable.
When none of the above methods is used the local build is performed and
the object files are placed in the source directory.
|
| |
| |
| |
| |
| |
| | |
Patch by Andy Fleming 17-Mar-2006
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
| |
| |
| |
| |
| |
| |
| | |
* Added support for PCI2 on CDS
Patch by Andy Fleming 17-Mar-2006
Signed-off-by: Andy Fleming <afleming@freescale.com>
|
|/
|
|
|
|
| |
Loeliger 17-Jan-2006
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
| |
|
|
|
|
|
| |
Pointed out by Gerhard Jaeger, 31 Aug 2005;
cf. http://sourceware.org/ml/binutils/2005-08/msg00412.html
|
|
|
|
|
| |
Move the TSEC driver out of cpu/mpc85xx as it will be shared
by the upcoming mpc83xx family as well.
|
|
|
|
|
|
|
|
| |
Implemented support for MPC8548CDS board.
Added DDR II support based on SPD values for MPC85xx boards.
This roll-up patch also includes bugfies for the previously
published patches:
DDRII CPO, pre eTSEC, 8548 LBIU, Andy's TSEC, eTSEC 3&4 I/O
|
|
|
|
|
|
|
| |
Add missing PCI IO port definitions.
author Kumar Gala <kumar.gala@freescale.com> Wed, 20 Jul 2005 15:39:52 -0500
committer Jon Loeliger <jdl@freescale.com> Wed, 20 Jul 2005 15:39:52 -0500
|
|
|
|
|
|
| |
- Add support for Altera Nios-II processors.
- Add support for Psyent PCI-5441 board.
- Add support for Psyent PK1C20 board.
|
|
- Add support for the MPC8541 and MPC8555 CDS boards
- Cleanup eth?addr handling: make dependent on CONFIG_ETH?ADDR
|