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* | ppc4xx/fdt/flash: Change fdt_fixup_nor_flash_node() to not rely on cs sizeStefan Roese2010-09-23-0/+31
|/ | | | | | | | | | | | | | | | | | | | | | This patch changes the behaviour of the fdt_fixup_nor_flash_node() function. Now it doesn't patch the size of the "reg" property with the chip-select size, but with the size returned from the new function flash_get_bank_size(). This function will return per weak default the flash size of the bank (bank = chip-select numer) detected by the flash driver. If this does not fit your needs, this function may be overridden by a board specific one. For this the parameters needed to be changed. So I intentionally squashed the PPC4xx stuff using this routine into this patch. Otherwise it would not be git-bisectable anymore. The board specific function for the AMCC/APM Ebony eval board is now included in this patch version. Signed-off-by: Stefan Roese <sr@denx.de> Tested-by: Detlev Zundel <dzu@denx.de> Cc: Gerald Van Baren <vanbaren@cideas.com> Cc: Wolfgang Denk <wd@denx.de>
* cmd_usage(): simplify return code handlingWolfgang Denk2010-07-24-51/+32
| | | | | | | | | | | | | | | | Lots of code use this construct: cmd_usage(cmdtp); return 1; Change cmd_usage() let it return 1 - then we can replace all these ocurrances by return cmd_usage(cmdtp); This fixes a few places with incorrect return code handling, too. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx/Canyonlands added USB board callbacksRupjyoti Sarmah2010-07-23-9/+55
| | | | | | | | | | Functions added to support board callbacks for USB init. This isolates USB manipulations such that it is only touched if USB is used by U-Boot. Signed-off-by: Dave Mitchell <dmitchell@appliedmicro.com> Signed-off-by: Rupjyoti Sarmah <rsarmah@appliedmicro.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Make sure that argv[] argument pointers are not modified.Wolfgang Denk2010-07-04-24/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The hush shell dynamically allocates (and re-allocates) memory for the argument strings in the "char *argv[]" argument vector passed to commands. Any code that modifies these pointers will cause serious corruption of the malloc data structures and crash U-Boot, so make sure the compiler can check that no such modifications are being done by changing the code into "char * const argv[]". This modification is the result of debugging a strange crash caused after adding a new command, which used the following argument processing code which has been working perfectly fine in all Unix systems since version 6 - but not so in U-Boot: int main (int argc, char **argv) { while (--argc > 0 && **++argv == '-') { /* ====> */ while (*++*argv) { switch (**argv) { case 'd': debug++; break; ... default: usage (); } } } ... } The line marked "====>" will corrupt the malloc data structures and usually cause U-Boot to crash when the next command gets executed by the shell. With the modification, the compiler will prevent this with an error: increment of read-only location '*argv' N.B.: The code above can be trivially rewritten like this: while (--argc > 0 && **++argv == '-') { char *arg = *argv; while (*++arg) { switch (*arg) { ... Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2010-04-24-256/+162
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| * ppc4xx: TLB init file cleanupStefan Roese2010-04-19-256/+162
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds new macros, with frequently used combinations of the 4xx TLB access control and storage attibutes. Additionally the 4xx init.S files are updated to make use of these new macros. Resulting in easier to read TLB definitions. Additionally some init.S files are updated to use the mmu header for the TLB defines, instead of defining their own macros. Signed-off-by: Stefan Roese <sr@denx.de>
* | Move arch/ppc to arch/powerpcStefan Roese2010-04-21-11/+11
|/ | | | | | | | | | | | | | | | | As discussed on the list, move "arch/ppc" to "arch/powerpc" to better match the Linux directory structure. Please note that this patch also changes the "ppc" target in MAKEALL to "powerpc" to match this new infrastructure. But "ppc" is kept as an alias for now, to not break compatibility with scripts using this name. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Acked-by: Detlev Zundel <dzu@denx.de> Acked-by: Kim Phillips <kim.phillips@freescale.com> Cc: Peter Tyser <ptyser@xes-inc.com> Cc: Anatolij Gustschin <agust@denx.de>
* ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser2010-04-13-11/+11
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Replace "#include <asm-$ARCH/$FILE>" with "#include <asm/$FILE>"Peter Tyser2010-04-13-10/+10
| | | | | | | | | | The appropriate include/asm-$ARCH directory should already by symlinked to include/asm so using the whole "asm-$ARCH" path is unnecessary. This change should also allow us to move the include/asm-$ARCH directories into their appropriate lib/$ARCH/ directories. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Kilauea: Add CPLD version detection and EBC reconfigurationStefan Roese2010-01-23-1/+39
| | | | | | | | | | | | | | | A newer CPLD version on the 405EX evaluation board requires a different EBC controller setup for the CPLD register access. This patch adds a CPLD version detection for Kilauea and code to reconfigure the EBC controller (chip select 2) for the old CPLD if no new version is found. Additionally the CPLD version is printed upon bootup: Board: Kilauea - AMCC PPC405EX Evaluation Board (CPLD rev. 0) Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de> Cc: Zhang Bao Quan <bqzhang@udtech.com.cn>
* PCIe, USB: Replace 'end point' references with 'endpoint'Peter Tyser2010-01-17-1/+1
| | | | | | | | | When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
* POST: Remove duplicated post_hotkey_pressed() functionsStefan Roese2009-12-07-78/+0
| | | | | | | | | | | | | This patch introduces a weak default function for post_hotkey_pressed(), returning 0, for boards without hotkey support. The long-running tests won't be started on those boards. This default function was implemented in many board directories. By implementing this weak default we can remove all those duplicate versions. Boards with hotkey support, can override this weak default function by defining one in their board specific code. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate pci_master_init() functionStefan Roese2009-11-19-59/+0
| | | | | | | | This patch removes the duplicted implementations of the pci_master_init() function by introducing a weak default function for it. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate pci_pre_init() functionStefan Roese2009-11-19-395/+1
| | | | | | | | | This patch removes the duplicted implementations of the pci_pre_init() function by introducing a weak default function for it. This weak default has a different implementation for some PPC variants. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate pci_target_init() functionStefan Roese2009-11-19-459/+1
| | | | | | | | | | This patch removes the duplicted implementations of the pci_target_init() function by introducing a weak default function for it. This weak default has a different implementation for 440EP(x)/GR(x) PPC's. It can be overridden by a board specific version (e.g. PMC440, korat). Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* ppc4xx: Katmai: Add chip_config commandStefan Roese2009-11-10-219/+58
| | | | | | | This patch removes the Katmai "bootstrap" command and replaces it with the now common command "chip_config". Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix NAND booting targets after 4xx linker script consolidationStefan Roese2009-11-09-0/+20
| | | | | | | Somehow I missed the NAND booting targets in the 4xx linker script consolidation patchset. This patch fixes this issue. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove duplicated is_pci_host() functionsStefan Roese2009-11-09-221/+0
| | | | | | | | | This patch introduces a weak default function for is_pci_host(), returning 1. This is the default behaviour, since most boards only implement PCI host functionality. This weak default can be overridden by a board specific version if needed. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate 4xx PCIe board specific configurationStefan Roese2009-11-09-442/+41
| | | | | | | | | This patch consolidates the PPC4xx board specific PCIe configuration code. This way the duplicated code is removed. Boards can implement a special, non standard behaviour (e.g. number of PCIe slots, etc) by overriding the weak default functions. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove board specific linker scripts from most PPC4xx boardsStefan Roese2009-11-02-2360/+0
| | | | | | | | | All these linker scripts can be removed since the new common ppc4xx linker script should be able to handle all of those boards. Please test and report problems. Thanks. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Sequoia: Add chip_config commandStefan Roese2009-10-23-232/+125
| | | | | | | | | | | | | | | This patch removes the Sequoia "bootstrap" command and replaces it with the now common command "chip_config". Please note that the patches with the dynamic PCI sync clock configuration have to be applied, before this one should go in. This is because Sequoia has 2 different bootstrap EEPROMs, and the old bootstrap command configured different values depending on the detected PCI async clock (33 vs. 66MHz). With the PCI sync clock patches, this is not necessary anymore. The PCI sync clock will be configured correctly on-the-fly now. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Yosemite/Yellowstone: Check and reconfigure the PCI sync clockStefan Roese2009-10-23-3/+23
| | | | | | | This patch now uses the 440EP(x)/GR(x) function to check and dynamically reconfigure the PCI sync clock. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Sequoia/Rainer: Check and reconfigure the PCI sync clockStefan Roese2009-10-23-3/+23
| | | | | | | This patch now uses the 440EP(x)/GR(x) function to check and dynamically reconfigure the PCI sync clock. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'reloc'Wolfgang Denk2009-10-09-23/+0
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| * ppc: Enable full relocation to RAMPeter Tyser2009-10-03-23/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | ppc_4xx: Apply new HW register namesNiklaus Giger2009-10-07-190/+190
| | | | | | | | | | | | | | | | Modify all existing *.c files to use the new register names as seen in the AMCC manuals. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix msg "initialization as root-complex failed" upon PCIe scanStefan Roese2009-10-07-0/+15
|/ | | | | | | | | | This message is printed upon PCIe bus scan, not only upon error, but also if no PCIe device is detected at all. Since this is not an error, let's remove this message in this case. We already have the message "link is not up." if there is no PCIe device present. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper caseStefan Roese2009-09-28-40/+40
| | | | | | | | | The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Convert PPC4xx UIC defines from lower case to upper caseStefan Roese2009-09-28-349/+349
| | | | | | | The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-09-15-309/+309
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| * ppc4xx: Big cleanup of PPC4xx definesStefan Roese2009-09-11-309/+309
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
* | board/amcc/common/flash.c: Fix compile warningWolfgang Denk2009-09-15-3/+4
| | | | | | | | | | | | | | | | | | Fix warning: ../common/flash.c:917: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* | board/amcc/yucca/flash.c: Fix compile warningWolfgang Denk2009-09-15-3/+4
| | | | | | | | | | | | | | | | | | Fix warning: flash.c:919: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* | board/amcc/taihu/flash.c: Fix compile warningWolfgang Denk2009-09-15-6/+8
|/ | | | | | | | | | | | Fix warnings: flash.c: In function 'write_word_1': flash.c:696: warning: dereferencing type-punned pointer will break strict-aliasing rules flash.c: In function 'write_word_2': flash.c:1044: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix "chip_config" command for AMCC ArchesStefan Roese2009-08-18-16/+18
| | | | | | | | | | This patch fixes the "chip_config" command for I2C bootstrap EEPROM configuration. First it changes the I2C bootstrap EEPROM address to 0x54 as this is used on Arches (instead of 0x52 on Canyonlands/ Glacier). Additionally, the NAND bootstrap settings are removed for Arches since Arches doesn't support NAND-booting. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add support for PPC460EX/460GT rev B chip to AMCC CanyonlandsStefan Roese2009-07-30-9/+17
| | | | | | | This patch is based on a diff created by Phong Vo from AMCC. Signed-off-by: Phong Vo <pvo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix problem with NOR range assignment in Canyonlands ft_board_setupStefan Roese2009-07-28-15/+0
| | | | | | | | | | | This patch fixes the problem, that the current fdt board fixup code only set's one range, the one for NOR. By this it's overwriting the already correctly configured values done in __ft_board_setup(). Just remove this now unneeded NOR fixup and all the ranges are correctly defined. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Felix Radensky <felix@embedded-sol.com>
* ppc4xx: Add some NAND-booting bootstrap entries to Kilauea chip_config cmdStefan Roese2009-07-28-4/+20
| | | | | | | | | This patch adds some I2C bootstrap setting for NAND booting to the Kilauea chip_config command ("533-nand" and "600-nand"). Additionally some incorrectly indented lines are fixed. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix Arches DDR2 initializationStefan Roese2009-07-28-12/+18
| | | | | | | | | Testing on AMCC Arches with the latest U-Boot version yielded that DDR2 initialization is currently broken. U-Boot hangs upon relocation to SDRAM or crashes with random traps. This patch fixes this problem. Arches now uses a different WRDTR and CLKTR default setting than Canyonlands/Glacier. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add chip_config command to AMCC Kilauea eval boardStefan Roese2009-07-24-298/+76
| | | | | | | | This patch removes the "alterpll" command and replaces it with the now ppc4xx standard "chip_config" command to configure the I2C bootstrap EEPROM. Signed-off-by: Stefan Roese <sr@denx.de>
* Add "chip_config" command for PPC4xx bootstrap configurationStefan Roese2009-07-24-197/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a generic command for programming I2C bootstrap eeproms on PPC4xx. An implementation for Canyonlands board is included. The command name is intentionally chosen not to be PPC4xx specific. This way other CPU's/SoC's can implement a similar command under the same name, perhaps with a different syntax. Usage on Canyonlands: => chip_config Available configurations (I2C address 0x52): 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 600-nand - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100 800-nor - NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100 800-nand - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100 1000-nand - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100 1066-nor - NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88 *** 1066-nand - NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88 => chip_config 600-nor Using configuration: 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 done (dump via 'i2c md 52 0.1 10') Reset the board for the changes to take effect Other 4xx boards will be migrated to use this command soon as well. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Dirk Eibach <eibach@gdsys.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* ppc4xx: Fix FDT EBC mappings on CanyonlandsFelix Radensky2009-07-08-2/+4
| | | | | | | | | | This patch fixes 2 problems with FDT EBC mappings on Canyonlands. First, NAND EBC mapping was missing, making Linux NAND driver unusable on this board. Second, NOR remapping code assumed that NOR is always on CS0, however when booting from NAND NOR is on CS3. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* General help message cleanupWolfgang Denk2009-06-12-40/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many of the help messages were not really helpful; for example, many commands that take no arguments would not print a correct synopsis line, but "No additional help available." which is not exactly wrong, but not helpful either. Commit ``Make "usage" messages more helpful.'' changed this partially. But it also became clear that lots of "Usage" and "Help" messages (fields "usage" and "help" in struct cmd_tbl_s respective) were actually redundant. This patch cleans this up - for example: Before: => help dtt dtt - Digital Thermometer and Thermostat Usage: dtt - Read temperature from digital thermometer and thermostat. After: => help dtt dtt - Read temperature from Digital Thermometer and Thermostat Usage: dtt Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Add Sequoia RAM-booting targetStefan Roese2009-06-12-3/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds another build target for the AMCC Sequoia PPC440EPx eval board. This RAM-booting version is targeted for boards without NOR FLASH (NAND booting) which need a possibility to initially program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000) configured to setup the SDRAM, this debugger can load this RAM- booting image to the target address in SDRAM (in this case 0x1000000) and start it there. Then U-Boot's standard NAND commands can be used to program the NAND FLASH (e.g. "nand write ..."). Here the commands to load and start this image from the BDI2000: 440EPX>reset halt 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin 440EPX>go 0x1000000 Please note that this image automatically scans for an already initialized SDRAM TLB (detected by EPN=0). This TLB will not be cleared. This TLB doesn't need to be TLB #0, this RAM-booting version will detect it and preserve it. So booting via BDI2000 will work and booting with a complete different TLB init via U-Boot works as well. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove unused code for Sequoia NAND booting versionStefan Roese2009-04-16-5/+1
| | | | | | | | The current define of get_bus_freq() in the CONFIG_NAND_SPL #ifdef is not used at all. This patch changes it's define to the currently used value of 133333333 and removes the unnecessary code. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fixup chip-selects in dtb for NAND-booting SequoiaStefan Roese2009-04-16-2/+56
| | | | | | | | | | | | | | | | | | | | Currently the NOR & NAND support in Linux only works for the "standard" Sequoia, the version booting for NOR flash. The NAND-booting version has the chip-selects swapped. Here the chip-select mappings: "Standard" NOR-booting version: CS0 NOR CS3 NAND NAND-booting version: CS0 NAND CS3 NOR With this path the dtb gets fixed-up, so that the correct chip-select numbers are patched in the dtb enabling correct NOR & NAND support in Linux on the NAND-booting Sequoia version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Sequoia: Fix TLB reassignment in NAND booting codeStefan Roese2009-03-26-1/+1
| | | | | | | | | | This patch fixes a bug in the Sequoia TLB init code to reconfigure the correct TLB (boot space) after running from RAM. This bug was introduced with patch 4d332dbeb08f5863d1ea69d91a00c5499d3a87ed [ppc4xx: Make Sequoia boot vxWorks] which changed the order of the TLB in the Sequoia init.S file. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix all linker script to handle all rodata sectionsTrent Piepho2009-03-20-66/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
* Fix AMCC Sequoia board DDR memory configurationMikhail Zolotaryov2009-03-17-1/+1
| | | | | | | | | | | | | | | Sequoia board schematics (DES0211_11_SCH_11.pdf, page 5, unit U1D) specifies that BankSel#1 is not connected, while bootloader memory configuration is (board/amcc/sequoia/sdram.c): mtsdram(DDR0_10, 0x00000300); i.e. both Chip Selects used - not correct. If we change to correct value here: mtsdram(DDR0_10, 0x00000100); memory is accessible OK also. Signed-off-by: Mikhail Zolotaryov <lebon@lebon.org.ua> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix problem with board_eth_init() vs cpu_eth_init() on AMCC boardsStefan Roese2009-02-12-0/+4
| | | | | | | | Some AMCC eval boards do have a board_eth_init() function calling pci_eth_init(). These boards need to call cpu_eth_init() explicitly now with the new eth_init rework. Signed-off-by: Stefan Roese <sr@denx.de>
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