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* ppc4xx: Sequoia: Fix TLB reassignment in NAND booting codeStefan Roese2009-03-26-1/+1
| | | | | | | | | | This patch fixes a bug in the Sequoia TLB init code to reconfigure the correct TLB (boot space) after running from RAM. This bug was introduced with patch 4d332dbeb08f5863d1ea69d91a00c5499d3a87ed [ppc4xx: Make Sequoia boot vxWorks] which changed the order of the TLB in the Sequoia init.S file. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix all linker script to handle all rodata sectionsTrent Piepho2009-03-20-66/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
* Fix AMCC Sequoia board DDR memory configurationMikhail Zolotaryov2009-03-17-1/+1
| | | | | | | | | | | | | | | Sequoia board schematics (DES0211_11_SCH_11.pdf, page 5, unit U1D) specifies that BankSel#1 is not connected, while bootloader memory configuration is (board/amcc/sequoia/sdram.c): mtsdram(DDR0_10, 0x00000300); i.e. both Chip Selects used - not correct. If we change to correct value here: mtsdram(DDR0_10, 0x00000100); memory is accessible OK also. Signed-off-by: Mikhail Zolotaryov <lebon@lebon.org.ua> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix problem with board_eth_init() vs cpu_eth_init() on AMCC boardsStefan Roese2009-02-12-0/+4
| | | | | | | | Some AMCC eval boards do have a board_eth_init() function calling pci_eth_init(). These boards need to call cpu_eth_init() explicitly now with the new eth_init rework. Signed-off-by: Stefan Roese <sr@denx.de>
* Command usage cleanupPeter Tyser2009-01-28-26/+26
| | | | | | | | Remove command name from all command "usage" fields and update common/command.c to display "name - usage" instead of just "usage". Also remove newlines from command usage fields. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* amcc: Clean up command usage outputPeter Tyser2009-01-28-9/+9
| | | | | | | Update taihu and taishan commands to use cmd_usage() function to display usage messages. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Standardize command usage messages with cmd_usage()Peter Tyser2009-01-28-12/+12
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initializationDave Mitchell2008-11-21-1/+1
| | | | | | | | | | | | | | | | | | Expanded OCM TLB to allow access to 64K OCM as well as 256K of internal SRAM. Adjusted internal SRAM initialization to match updated user manual recommendation. OCM & ISRAM are now mapped as follows: physical virtual size ISRAM 0x4_0000_0000 0xE300_0000 256k OCM 0x4_0004_0000 0xE304_0000 64k A single TLB was used for this mapping. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRsDave Mitchell2008-11-21-11/+12
| | | | | | | | | | | Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and L2 cache DCRs from ppc440.h to this new header. Also converted these DCR defines from lowercase to uppercase and modified referencing modules to use them. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Align end of bss by 4 bytesSelvamuthukumar2008-11-18-0/+22
| | | | | | | | | | Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup, update CHANGELOGWolfgang Denk2008-11-02-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-10-21-0/+169
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| * ppc4xx: Add 1.0 & 1.066 GHz to canyonlands bootstrap command for PLL setupStefan Roese2008-10-21-0/+12
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add AMCC Arches board support (dual 460GT)Adam Graham2008-10-21-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-20/+20
|/ | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-761/+761
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ppc4xx: Canyonlands: Remove unnecessary FDT warning upon DTB fixupStefan Roese2008-09-22-12/+4
| | | | | | | | | Depending on the configuration jumper "SATA SELECT", U-Boot disabled either one PCIe node or the SATA node in the device tree blob. This patch removes the unnecessary and even confusing warning, when the node is not found at all. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'Makefile-next' of git://git.denx.de/u-boot-armWolfgang Denk2008-09-12-55/+53
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| * rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-36/+36
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * move cmd_get_data_size to command.cJean-Christophe PLAGNIOL-VILLARD2008-09-10-2/+0
| | | | | | | | | | | | add CMD_DATA_SIZE macro to enable it Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASHJean-Christophe PLAGNIOL-VILLARD2008-09-10-12/+12
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * rename environment.c in env_embedded.c to reflect is functionalityJean-Christophe PLAGNIOL-VILLARD2008-09-10-6/+6
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ppc4xx: Fix SDRAM inititialization of multiple 405 based board portsStefan Roese2008-09-12-9/+0
|/ | | | | | | | | | | | | | | This patch fixes a problem introdiced with patch bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by initdram()]. The boards affected are: - PCI405 - PPChameleonEVB - quad100hd - taihu - zeus Signed-off-by: Stefan Roese <sr@denx.de>
* Moved initialization of EEPRO100 Ethernet controller to board_eth_init()Ben Warren2008-09-02-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards: db64360 db64460 katmai taihu taishan yucca cpc45 cpu87 eXalion elppc debris kvme080 mpc8315erdb integratorap ixdp425 oxc pm826 pm828 pm854 pm856 ppmc7xx sc3 sc520_spunk sorcery tqm8272 tqm85xx utx8245 Removed initialization of the driver from net/eth.c Also, wrapped contents of pci_eth_init() by CONFIG_PCI. Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-08-12-0/+5
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| * ppc4xx: Sequoia has two UARTs in "4-pin" mode. Configure the GPIOs as per ↵Steven A. Falco2008-08-07-0/+5
| | | | | | | | | | | | | | | | | | | | | | schematic. The Sequoia board has two UARTs in "4-pin" mode. This patch modifies the GPIO configuration to match the schematic, and also sets the SDR0_PFC1 register to select the corresponding mode for the UARTs. Signed-off-by: Steven A. Falco <sfalco@harris.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-07-14-55/+55
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| * ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boardsStefan Roese2008-07-13-105/+0
| | | | | | | | | | | | | | | | | | This patch removes some ft_board_setup() functions from some 4xx boards. This can be done since we now have a default weak implementation for this in cpu/ppc4xx/fdt.c. Only board in need for a different/custom implementation like canyonlands need their own version. Signed-off-by: Stefan Roese <sr@denx.de>
| * Fix some more printf() format issues.Wolfgang Denk2008-07-11-55/+55
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ppc4xx: Some Rewood cleanups (coding style, leading white spaces)Stefan Roese2008-07-11-177/+141
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Cleanup Katmai & Yucca PCIe register usageStefan Roese2008-07-11-126/+8
| | | | | | | | | | | | | | This patch cleans up the 440SPe PCIe register usage. Now only defines from the include/asm-ppc/4xx_pcie.h are used. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Rework 440GX UIC handlingStefan Roese2008-07-11-38/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch reworks the 440GX interrupt handling so that the common 4xx code can be used. The 440GX is an exception to all other 4xx variants by having the cascading interrupt vectors not on UIC0 but on a special UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt handling is simpler without any 440GX special cases. Also some additional cleanup to cpu/ppc4xx/interrupt.c is done. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate PPC4xx UIC definesStefan Roese2008-07-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This 2nd patch now removes all UIC mask bit definition. They should be generated from the vectors by using the UIC_MASK() macro from now on. This way only the vectors need to get defined for new PPC's. Also only the really used interrupt vectors are now defined. This makes definitions for new PPC versions easier and less error prone. Another part of this patch is that the 4xx emac driver got a little cleanup, since now the usage of the interrupts is clearer. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate PPC4xx UIC definesStefan Roese2008-07-11-2/+1
| | | | | | | | | | | | | | | | | | This patch is the first step to consolidate the UIC related defines in the 4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next steps. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boardsStefan Roese2008-07-11-105/+0
| | | | | | | | | | | | | | | | | | This patch removes some ft_board_setup() functions from some 4xx boards. This can be done since we now have a default weak implementation for this in cpu/ppc4xx/fdt.c. Only board in need for a different/custom implementation like canyonlands need their own version. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Initial framework of the AMCC PPC460SX redwood reference board.Feng Kan2008-07-11-0/+858
|/ | | | | | | | | | Add AMCC Redwood reference board that uses the latest PPC 464 CPU processor combined with a rich mix of peripheral controllers. The board will support PCIe, mutiple Gig ethernet ports, advanced hardware RAID assistance and IEEE 1588. Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix printf format warnings now visible with the updated format checkStefan Roese2008-07-10-2/+2
| | | | | | | | | This patch fixes ppc4xx related printf format warning. Those warnings are now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd [Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is really helpful. Signed-off-by: Stefan Roese <sr@denx.de>
* Cleanup: remove redundant deleting on *~ filesWolfgang Denk2008-07-02-6/+6
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Cleanup out-or-tree building for some boards (.depend)Wolfgang Denk2008-07-02-16/+16
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Canyonlands: Disable the RTC M41T62 square wave outputStefan Roese2008-06-12-0/+11
| | | | | | | | | | | | | | | | | This patch disables the square wave output of the M41T62 RTC used on Canyonlands & Glacier. Here the explanation: The serial real-time clock part used in the design is an STMicro M41T62. This part has a full-time 32KHz square wave output that is connected to the TmrClk input to the processor. The default state for this square wave output is enabled so the output runs continuously when the board is powered normally and also from the battery. The TmrClk input to the processor goes to ground when the power is removed from the board/processor, and therefore the running square wave output is driving ground which drains the battery quickly. Signed-off-by: Stefan Roese <sr@denx.de>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-12-11/+11
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk2008-06-11-1020/+13
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| * ppc4xx: Unify AMCC's board config files (part 3/3)Stefan Roese2008-06-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch series unifies the AMCC eval board ports by introducing a common include header for all AMCC eval boards: include/configs/amcc-common.h This header now includes all common configuration options/defines which are removed from the board specific headers. The reason for this is ease of maintenance and unified look and feel of all AMCC boards. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Remove implementations of testdram()Stefan Roese2008-06-03-379/+0
| | | | | | | | | | | | | | This patch removes the used testdram() implementations of the board that are maintained by myself. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Remove superfluous dram_init() call or replace it by initdram()Stefan Roese2008-06-03-101/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically the 405 U-Boot port had a dram_init() call in early init stage. This function was still called from start.S and most of the time coded in assembler. This is not needed anymore (since a long time) and boards should implement the common initdram() function in C instead. This patch now removed the dram_init() call from start.S and removes the empty implementations that are scattered through most of the 405 board ports. Some older board ports really implement this dram_init() though. These are: csb272 csb472 ERIC EXBITGEN W7OLMC W7OLMG I changed those boards to call this assembler dram_init() function now from their board specific initdram() instead. This *should* work, but please test again on those platforms. And it is perhaps a good idea that those boards use some common 405 SDRAM initialization code from cpu/ppc4xx at some time. So further patches welcome here. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Change Kilauea to use the common DDR2 init functionStefan Roese2008-06-03-253/+1
| | | | | | | | | | | | | | | | | | | | | | This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used. Thanks to Grant Erickson for all his basic work on this 405EX early bootup. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Enable Primordial Stack for 40x and Unify ECC HandlingGrant Erickson2008-06-03-417/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch (Part 2 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | SPI API improvementsHaavard Skinnemoen2008-06-03-6/+10
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gets rid of the spi_chipsel table and adds a handful of new functions that makes the SPI layer cleaner and more flexible. Instead of the spi_chipsel table, each board that wants to use SPI gets to implement three hooks: * spi_cs_activate(): Activates the chipselect for a given slave * spi_cs_deactivate(): Deactivates the chipselect for a given slave * spi_cs_is_valid(): Determines if the given bus/chipselect combination can be activated. Not all drivers may need those extra functions however. If that's the case, the board code may just leave them out (assuming they know what the driver needs) or rely on the linker to strip them out (assuming --gc-sections is being used.) To set up communication parameters for a given slave, the driver needs to call spi_setup_slave(). This returns a pointer to an opaque spi_slave struct which must be passed as a parameter to subsequent SPI calls. This struct can be freed by calling spi_free_slave(), but most driver probably don't want to do this. Before starting one or more SPI transfers, the driver must call spi_claim_bus() to gain exclusive access to the SPI bus and initialize the hardware. When all transfers are done, the driver must call spi_release_bus() to make the bus available to others, and possibly shut down the SPI controller hardware. spi_xfer() behaves mostly the same as before, but it now takes a spi_slave parameter instead of a spi_chipsel function pointer. It also got a new parameter, flags, which is used to specify chip select behaviour. This may be extended with other flags in the future. This patch has been build-tested on all powerpc and arm boards involved. I have not tested NIOS since I don't have a toolchain for it installed, so I expect some breakage there even though I've tried fixing up everything I could find by visual inspection. I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and DataFlash drivers posted as a follow-up. I'd like some help testing other boards that use the existing SPI API. But most of all, I'd like some comments on the new API. Is this stuff usable for everyone? If not, why? Changed in v4: - Build fixes for various boards, drivers and commands - Provide common struct spi_slave definition that can be extended by drivers - Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate - Make default bus and mode build-time configurable - Override default SPI bus ID and mode on mx32ads and imx31_litekit. Changed in v3: - Add opaque struct spi_slave for controller-specific data associated with a slave. - Add spi_claim_bus() and spi_release_bus() - Add spi_free_slave() - spi_setup() is now called spi_setup_slave() and returns a struct spi_slave - soft_spi now supports four SPI modes (CPOL|CPHA) - Add bus parameter to spi_setup_slave() - Convert the new i.MX32 SPI driver - Convert the new MC13783 RTC driver Changed in v2: - Convert the mpc8xxx_spi driver and the mpc8349emds board to the new API. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Tested-by: Guennadi Liakhovetski <lg@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-195/+195
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Canyonlands: Disable PCIe0/SATA in dev-tree depending on selectionStefan Roese2008-05-19-1/+30
| | | | | | | | | | | | | | | When SATA is selected (via jumper J6) we need to disable the first PCIe node in the device tree, so that Linux doesn't initialize it. Otherwise the Linux SATA driver will fail to detect the devices. The same goes the other way around too. So if PCIe is selected we need to disable the SATA node in the device tree. This is because PCIe port 0 and SATA on 460EX share the same pins (multiplexed) and we have to configure in U-Boot which peripheral is enabled. Signed-off-by: Stefan Roese <sr@denx.de>
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