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* ppc4xx: 405EX: Correctly enable USB pinsStefan Roese2007-12-08-0/+16
| | | | | | | | This patch selects the USB data pins in the 405EX GPIO and MFC (multi function control) registers. This is done for the AMCC Kilauea and Makalu eval boards. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable hardware-fix for PCI/DMA errata on AMCC 440SP/SPe boardsStefan Roese2007-12-06-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by setting the FIXD bit in the SDR0_MFR register. Here a description of the symptoms: Problem Description ------------------------------ If a DMA is performed between memory and PCI with the DMA 1 Controller using prefetch, and as a result uses a special purpose buffer selected by the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29), the first part of the transfer sequence is performed twice. The PPC440SPe PCI Controller requests more data than was needed such that in the case of enforce memory protection, a host CPU exception can occur. No data is corrupted, because data transfer is stopped in the PCI Controller. Prefetch enable is specified by setting DMA Configuration Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0. Behavior that may be observed in a running system --------------------------------------------------------------------------- 1. DMA performance is decreased because of the double access on the PCI bus interface. 2. If an illegal access to some address on the PCI bus is detected at the system level, a machine check or similar system error may occur. Workarounds Available ---------------------------------- 1. Do not program prefetch. Note that a prefetch command cannot be programmed without selecting a special purpose buffer. 2. To avoid crossing a physical boundary of the PCI slave device, add 512 bytes of address to the PCI address range. This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com> from AMCC and slighly changed. Signed-off-by: Pravin M. Bathija <pbathija@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Kilauea: Add PCIe reset assertion upon power-upStefan Roese2007-11-30-9/+6
| | | | | | | | This manual PCIe reset triggering solves the problem seen with the Intel EPRO/1000 card, which was not detected (link not established) upon power-up reset. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update AMCC Makalu for board rev 1.1Stefan Roese2007-11-16-54/+13
| | | | | | | | | | | This patch adds changes needed for Makalu rev 1.1: - Enable 2nd DDR2 bank resulting in 256MByte of SDRAM - Enable 2nd ethernet port EMAC1 - Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE) - Reset PCIe ports via GPIO upon bootup Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Small AMCC Kilauea cleanupStefan Roese2007-11-15-39/+0
| | | | | | Remove not needed pci_target_init() function. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make output a little shorter on PCIe detectionStefan Roese2007-11-05-17/+12
| | | | | | Now not max 3 lines but 2 lines are printed per PCIe port. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add AMCC Kilauea/Haleakala NAND booting supportStefan Roese2007-11-03-1/+148
| | | | | | | This patch adds NAND booting support for the AMCC 405EX(r) eval boards. Again, only one image supports both targets. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAMStefan Roese2007-10-31-0/+4
| | | | | | | | | | | | | | This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board supportStefan Roese2007-10-31-3/+33
| | | | | | | | | | The Haleakala is nearly identical with the Kilauea eval board. The only difference is that the 405EXr only supports one EMAC and one PCIe interface. This patch adds support for the Haleakala board by using the identical image for Kilauea and Haleakala. The distinction is done by comparing the PVR. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fixed offset of refresh rate type for Bamboo on-board DDR SDRAMEugene O'Brien2007-10-31-2/+2
| | | | | | | | | | | | | This patch also adds a note to the fixed DDR setup for Bamboo NAND booting: Note: As found out by Eugene O'Brien <eugene.obrien@advantechamt.com>, the fixed DDR setup has problems (U-Boot crashes randomly upon TFTP), when the DIMM modules are still plugged in. So it is recommended to remove the DIMM modules while using the NAND booting code with the fixed SDRAM setup! Signed-off-by: Eugene O'Brien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Rework of 4xx serial driver (2)Stefan Roese2007-10-31-250/+0
| | | | | | | | | | Change all linker scripts to reference the changed driver name 4xx_uart.o. Note: In most cased all these explicit referencing of these object files in the linker scripts is not neccessary. Only for manually embedded environment into the U-Boot image, which is not done is most cases. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add initial AMCC Makalu 405EX supportStefan Roese2007-10-31-0/+1228
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xxStefan Roese2007-10-31-13/+7
| | | | | | | | | | This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix size setup in Kilauea DDR2 init routineStefan Roese2007-10-31-26/+26
| | | | | | | | | The size was initilized wrong. Instead of 256MB, the DDR2 controller was setup to 512MB. Now the correct values is used. This patch also does a little cleanup and adds a comment here. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint modeStefan Roese2007-10-31-104/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable device tree support (fdt) on Kilauea per defaultStefan Roese2007-10-31-0/+14
| | | | | | | | | | | | | This patch enables the fdt support on the AMCC Kilauea eval board. Additionally now EBC ranges fdt fixup is included to support NOR FLASH mapping via the Linux physmap_of driver. This Kilauea port now support booting arch/ppc and arch/powerpc Linux kernels. The default environment "net_nfs" is for arch/ppc and "net_nfs_fdt" is for arch/powerpc. In the long run, arch/ppc support will be removed. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add initial AMCC Kilauea 405EX supportStefan Roese2007-10-31-0/+1125
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)Stefan Roese2007-10-31-14/+8
| | | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (2) This patch renames the functions from 440spe_ to 4xx_ with a little additional cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)Stefan Roese2007-10-31-8/+7
| | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (1) This patch renames the files from 440spe_pcie to 4xx_pcie Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap commandStefan Roese2007-10-18-1/+7
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix bug in I2C bootstrap values for Sequoia/RainierStefan Roese2007-10-15-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C bootstrap values that can be setup via the "bootstrap" command, were setup incorrect regarding the generation of the internal sync PCI clock. The values for PLB clock == 133MHz were slighly incorrect and the values for PLB clock == 166MHz were totally incorrect. This could lead to a hangup upon booting while PCI configuration scan. This patch fixes this issue and configures valid PCI divisor values for the sync PCI clock, with respect to the provided external async PCI frequency. Here the values of the formula in the chapter 14.2 "PCI clocking" from the 440EPx users manual: AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz 33MHz async PCI frequency: PLB = 133: => 32 <= 44.3 <= 65 (div = 3) PLB = 166: => 32 <= 55.3 <= 65 (div = 3) 66MHz async PCI frequency: PLB = 133: => 65 <= 66.5 <= 132 (div = 2) PLB = 166: => 65 <= 83 <= 132 (div = 2) Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & YosemiteStefan Roese2007-10-15-5/+9
| | | | | | | | | | | The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Coding style cleanupStefan Roese2007-10-02-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Program EPLD to force full duplex mode for PHY.Grzegorz Bernacki2007-10-02-5/+12
| | | | | | | EPLD forces modes of PHY operation. By default full duplex is turned off. This fix turns it on. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as globalWolfgang Denk2007-09-15-6/+6
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* [PPC440SPe] PCIe environment settings for Katmai and YuccaGrzegorz Bernacki2007-09-07-0/+24
| | | | | | | | | | | | - 'pciconfighost' is set by default in order to be able to scan bridges behind the primary host/PCIe - 'pciscandelay' env variable is recognized to allow for user-controlled delay before the PCIe bus enumeration; some peripheral devices require a significant delay before they can be scanned (e.g. LSI8408E); without the delay they are not detected Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* [PPC440SPe] Improve PCIe configuration space accessGrzegorz Bernacki2007-09-07-20/+22
| | | | | | | | | | | | | - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx SequoiaGary Jennejohn2007-08-31-0/+3
| | | | | | | | | | | | | | | | | | | | | The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese <sr@denx.de>. o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update Sequoia/Rainier bootstrap commandStefan Roese2007-08-16-48/+157
| | | | | | | As suggested by David Mitchell, here an update for the Sequoia/Rainier bootstrap command. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/zeusStefan Roese2007-08-14-1/+1947
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| * ppc4xx: Add initial Zeus (PPC405EP) board supportStefan Roese2007-08-14-1/+18
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add support for AMCC 405EP Taihu boardJohn Otken2007-07-26-0/+1929
| | | | | | | | Signed-off-by: John Otken <john@softadvances.com>
* | ppc4xx: Update AMCC Bamboo 440EP supportEugene OBrien2007-07-31-104/+240
|/ | | | | | | | | | | | | | | Changed storage type of cfg_simulate_spd_eeprom to const Changed storage type of gpio_tab to stack storage (Cannot access global data declarations in .bss until afer code relocation) Improved SDRAM tests to catch problems where data is not uniquely addressable (e.g. incorrectly programmed SDRAM row or columns) Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules Fixed AM29LV320DT (OpCode Flash) sector map Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setupStefan Roese2007-07-16-0/+7
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.cStefan Roese2007-07-16-0/+34
| | | | | | | The new boardspecific DDR2 controller configuration is used for the Yucca board. Now the Yucca board with 440SPe Rev. A chips is also supported. Signed-off-by: Stefan Roese <sr@denx.de>
* resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPXNiklaus Giger2007-07-04-72/+4
| | | | Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-06-25-7/+17
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| * Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk2007-06-22-7/+7
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| * Extend POST support for PPC440Igor Lisitsin2007-06-22-0/+10
| | | | | | | | | | | | | | Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
* | ppc4xx: Add pci_pre_init() for 405 boardsStefan Roese2007-06-25-33/+20
|/ | | | | | | | This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add bootstrap command for AMCC Sequoia (440EPx) eval boardStefan Roese2007-06-19-1/+112
| | | | | | | | | | | This patch adds a board command to configure the I2C bootstrap EEPROM values. Right now 533 and 667MHz are supported for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 533 nor ;to configure the board for 533MHz NOR booting => bootstrap 667 nand ;to configure the board for 667MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
* [ppc4xx] Fix problem with NAND booting on AMCC AcadiaStefan Roese2007-06-19-1/+14
| | | | | | | | The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
* [ppc4xx] Change board/amcc/acadia/cpr.c to pll.cStefan Roese2007-06-19-0/+0
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese2007-06-06-4/+263
| | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add missing file for Bamboo NAND booting supportStefan Roese2007-06-01-0/+137
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-109/+123
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| * ppc4xx: Update Sequoia NAND booting support with ECCStefan Roese2007-06-01-0/+4
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Prepare Bamboo port for NAND booting supportStefan Roese2007-06-01-109/+119
| | | | | | | | | | | | | | | | | | | | This patch updates the "normal" Bamboo NOR booting port, so that it is compatible with the coming soon NAND booting Bamboo port. It also enables the 2nd NAND flash on the Bamboo. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Undo Sequoia patch for dynamic EBC speed support of 83MHzStefan Roese2007-06-01-6/+0
| | | | | | | | | | | | | | | | This patch undoes the patch by Jeff Mann with commit-id ada4697d. As suggested by AMCC it is not recommended to dynamically change the EBC speed after bootup. So we undo this change to be on the safe side. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Update AMCC Acadia support for board revision 1.1Stefan Roese2007-05-24-1/+8
| | | | | | | | | | | | | | | | | | | | | | This patch updates the Acadia (405EZ) support for the new 1.1 board revision. It also adds support for NAND FLASH via the 4xx NDFC. Please note that the jumper J7 must be in position 2-3 for this NAND support. Position 1-2 is for NAND booting only. NAND booting support will follow later. Signed-off-by: Stefan Roese <sr@denx.de>
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