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* ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap commandStefan Roese2007-10-18-1/+7
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix bug in I2C bootstrap values for Sequoia/RainierStefan Roese2007-10-15-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C bootstrap values that can be setup via the "bootstrap" command, were setup incorrect regarding the generation of the internal sync PCI clock. The values for PLB clock == 133MHz were slighly incorrect and the values for PLB clock == 166MHz were totally incorrect. This could lead to a hangup upon booting while PCI configuration scan. This patch fixes this issue and configures valid PCI divisor values for the sync PCI clock, with respect to the provided external async PCI frequency. Here the values of the formula in the chapter 14.2 "PCI clocking" from the 440EPx users manual: AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz 33MHz async PCI frequency: PLB = 133: => 32 <= 44.3 <= 65 (div = 3) PLB = 166: => 32 <= 55.3 <= 65 (div = 3) 66MHz async PCI frequency: PLB = 133: => 65 <= 66.5 <= 132 (div = 2) PLB = 166: => 65 <= 83 <= 132 (div = 2) Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & YosemiteStefan Roese2007-10-15-5/+9
| | | | | | | | | | | The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Coding style cleanupStefan Roese2007-10-02-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Program EPLD to force full duplex mode for PHY.Grzegorz Bernacki2007-10-02-5/+12
| | | | | | | EPLD forces modes of PHY operation. By default full duplex is turned off. This fix turns it on. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as globalWolfgang Denk2007-09-15-6/+6
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* [PPC440SPe] PCIe environment settings for Katmai and YuccaGrzegorz Bernacki2007-09-07-0/+24
| | | | | | | | | | | | - 'pciconfighost' is set by default in order to be able to scan bridges behind the primary host/PCIe - 'pciscandelay' env variable is recognized to allow for user-controlled delay before the PCIe bus enumeration; some peripheral devices require a significant delay before they can be scanned (e.g. LSI8408E); without the delay they are not detected Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* [PPC440SPe] Improve PCIe configuration space accessGrzegorz Bernacki2007-09-07-20/+22
| | | | | | | | | | | | | - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx SequoiaGary Jennejohn2007-08-31-0/+3
| | | | | | | | | | | | | | | | | | | | | The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese <sr@denx.de>. o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update Sequoia/Rainier bootstrap commandStefan Roese2007-08-16-48/+157
| | | | | | | As suggested by David Mitchell, here an update for the Sequoia/Rainier bootstrap command. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/zeusStefan Roese2007-08-14-1/+1947
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| * ppc4xx: Add initial Zeus (PPC405EP) board supportStefan Roese2007-08-14-1/+18
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add support for AMCC 405EP Taihu boardJohn Otken2007-07-26-0/+1929
| | | | | | | | Signed-off-by: John Otken <john@softadvances.com>
* | ppc4xx: Update AMCC Bamboo 440EP supportEugene OBrien2007-07-31-104/+240
|/ | | | | | | | | | | | | | | Changed storage type of cfg_simulate_spd_eeprom to const Changed storage type of gpio_tab to stack storage (Cannot access global data declarations in .bss until afer code relocation) Improved SDRAM tests to catch problems where data is not uniquely addressable (e.g. incorrectly programmed SDRAM row or columns) Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules Fixed AM29LV320DT (OpCode Flash) sector map Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: AMCC Luan uses the new boardspecific DDR2 controller setupStefan Roese2007-07-16-0/+7
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Support for Yucca board with 440SPe Rev A added to 44x_spd_ddr2.cStefan Roese2007-07-16-0/+34
| | | | | | | The new boardspecific DDR2 controller configuration is used for the Yucca board. Now the Yucca board with 440SPe Rev. A chips is also supported. Signed-off-by: Stefan Roese <sr@denx.de>
* resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPXNiklaus Giger2007-07-04-72/+4
| | | | Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-06-25-7/+17
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| * Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk2007-06-22-7/+7
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| * Extend POST support for PPC440Igor Lisitsin2007-06-22-0/+10
| | | | | | | | | | | | | | Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
* | ppc4xx: Add pci_pre_init() for 405 boardsStefan Roese2007-06-25-33/+20
|/ | | | | | | | This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add bootstrap command for AMCC Sequoia (440EPx) eval boardStefan Roese2007-06-19-1/+112
| | | | | | | | | | | This patch adds a board command to configure the I2C bootstrap EEPROM values. Right now 533 and 667MHz are supported for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 533 nor ;to configure the board for 533MHz NOR booting => bootstrap 667 nand ;to configure the board for 667MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
* [ppc4xx] Fix problem with NAND booting on AMCC AcadiaStefan Roese2007-06-19-1/+14
| | | | | | | | The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
* [ppc4xx] Change board/amcc/acadia/cpr.c to pll.cStefan Roese2007-06-19-0/+0
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese2007-06-06-4/+263
| | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add missing file for Bamboo NAND booting supportStefan Roese2007-06-01-0/+137
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-109/+123
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| * ppc4xx: Update Sequoia NAND booting support with ECCStefan Roese2007-06-01-0/+4
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Prepare Bamboo port for NAND booting supportStefan Roese2007-06-01-109/+119
| | | | | | | | | | | | | | | | | | | | This patch updates the "normal" Bamboo NOR booting port, so that it is compatible with the coming soon NAND booting Bamboo port. It also enables the 2nd NAND flash on the Bamboo. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Undo Sequoia patch for dynamic EBC speed support of 83MHzStefan Roese2007-06-01-6/+0
| | | | | | | | | | | | | | | | This patch undoes the patch by Jeff Mann with commit-id ada4697d. As suggested by AMCC it is not recommended to dynamically change the EBC speed after bootup. So we undo this change to be on the safe side. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Update AMCC Acadia support for board revision 1.1Stefan Roese2007-05-24-1/+8
| | | | | | | | | | | | | | | | | | | | | | This patch updates the Acadia (405EZ) support for the new 1.1 board revision. It also adds support for NAND FLASH via the 4xx NDFC. Please note that the jumper J7 must be in position 2-3 for this NAND support. Position 1-2 is for NAND booting only. NAND booting support will follow later. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Run new sequoia boards with an EBC speed of 83MHzJeffrey Mann2007-05-16-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the Sequoia board does not boot with an EBC faster than 66MHz, the clock divider are changed after the initial boot process. This allows for maximum clocking speeds to be achieved on newer boards. Sequoia boards with 666.66 MHz processors require that the EBC divider be set to 3 in order to start the initial boot process at a slower EBC speed. After the initial boot process, the divider can be set back to 2, which will cause the boards to run at 83.333MHz. This is backward compatible with boards with 533.33 MHz processors, as these boards will already be set with an EBC divider of 2. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
* | ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND bootingStefan Roese2007-05-05-1/+9
|/ | | | | | | | Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big for the 4k NAND boot image so define bus_frequency to 133MHz here which is save for the refresh counter setup. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Bamboo: Use current NAND driver and *not* the legacy driverStefan Roese2007-04-29-94/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update Acadia to not setup PLL when booting via bootstrap EEPROMStefan Roese2007-04-18-3/+7
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change SysACE address on KatmaiStefan Roese2007-04-02-1/+1
| | | | | | | | With this new base address of the Xilinx SystemACE controller the Linux driver will be easier to adapt, since it can now be mapped via the "normal" ioremap() call. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-03-31-10/+12
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| * Code cleanup. Update CHANGELOGWolfgang Denk2007-03-21-22/+10
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* | ppc4xx: Update Katmai bootstrap commandStefan Roese2007-03-31-1/+3
| | | | | | | | | | | | | | Now the DDR2 frequency is also 2*PLB frequency when 166MHz PLB is selected. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix "bootstrap" command for Katmai boardStefan Roese2007-03-31-76/+25
| | | | | | | | | | | | | | | | The board specific "bootstrap" command is now fixed and can be used for the AMCC Katmai board to configure different CPU/PLB/OPB frequencies. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-24-1725/+73
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| * [PATCH] Add 4xx GPIO functionsStefan Roese2007-03-24-10/+2
| | | | | | | | | | | | | | This patch adds some 4xx GPIO functions. It also moves some of the common code and defines into a common 4xx GPIO header file. Signed-off-by: Stefan Roese <sr@denx.de>
| * [PATCH] Small Sequoia cleanupStefan Roese2007-03-24-2/+2
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * [PATCH] Clean up 40EZ/Acadia supportStefan Roese2007-03-24-1713/+69
| | | | | | | | | | | | | | This patch cleans up all the open issue of the preliminary Acadia support. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-21-0/+2257
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| * [PATCH] Add AMCC Acadia (405EZ) eval board supportStefan Roese2007-03-21-0/+2257
| | | | | | | | | | | | | | | | | | This patch adds support for the new AMCC Acadia eval board. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Use dynamic SDRAM TLB setup on AMCC Ebony eval boardStefan Roese2007-03-16-58/+19
| | | | | | | | | | | | | | | | Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix file mode of sequoia.cStefan Roese2007-03-08-0/+0
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Clear Sequoia/Rainier security engine reset bitsJohn Otken john@softadvances.com2007-03-08-0/+4
| | | | | | | | Signed-off-by: John Otken john@softadvances.com <john@softadvances.com>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-597/+94
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