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* ppc4xx: Consolidate 4xx PCIe board specific configurationStefan Roese2009-11-09-442/+41
| | | | | | | | | This patch consolidates the PPC4xx board specific PCIe configuration code. This way the duplicated code is removed. Boards can implement a special, non standard behaviour (e.g. number of PCIe slots, etc) by overriding the weak default functions. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove board specific linker scripts from most PPC4xx boardsStefan Roese2009-11-02-2360/+0
| | | | | | | | | All these linker scripts can be removed since the new common ppc4xx linker script should be able to handle all of those boards. Please test and report problems. Thanks. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Sequoia: Add chip_config commandStefan Roese2009-10-23-232/+125
| | | | | | | | | | | | | | | This patch removes the Sequoia "bootstrap" command and replaces it with the now common command "chip_config". Please note that the patches with the dynamic PCI sync clock configuration have to be applied, before this one should go in. This is because Sequoia has 2 different bootstrap EEPROMs, and the old bootstrap command configured different values depending on the detected PCI async clock (33 vs. 66MHz). With the PCI sync clock patches, this is not necessary anymore. The PCI sync clock will be configured correctly on-the-fly now. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Yosemite/Yellowstone: Check and reconfigure the PCI sync clockStefan Roese2009-10-23-3/+23
| | | | | | | This patch now uses the 440EP(x)/GR(x) function to check and dynamically reconfigure the PCI sync clock. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Sequoia/Rainer: Check and reconfigure the PCI sync clockStefan Roese2009-10-23-3/+23
| | | | | | | This patch now uses the 440EP(x)/GR(x) function to check and dynamically reconfigure the PCI sync clock. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'reloc'Wolfgang Denk2009-10-09-23/+0
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| * ppc: Enable full relocation to RAMPeter Tyser2009-10-03-23/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | ppc_4xx: Apply new HW register namesNiklaus Giger2009-10-07-190/+190
| | | | | | | | | | | | | | | | Modify all existing *.c files to use the new register names as seen in the AMCC manuals. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix msg "initialization as root-complex failed" upon PCIe scanStefan Roese2009-10-07-0/+15
|/ | | | | | | | | | This message is printed upon PCIe bus scan, not only upon error, but also if no PCIe device is detected at all. Since this is not an error, let's remove this message in this case. We already have the message "link is not up." if there is no PCIe device present. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper caseStefan Roese2009-09-28-40/+40
| | | | | | | | | The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Convert PPC4xx UIC defines from lower case to upper caseStefan Roese2009-09-28-349/+349
| | | | | | | The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-09-15-309/+309
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| * ppc4xx: Big cleanup of PPC4xx definesStefan Roese2009-09-11-309/+309
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
* | board/amcc/common/flash.c: Fix compile warningWolfgang Denk2009-09-15-3/+4
| | | | | | | | | | | | | | | | | | Fix warning: ../common/flash.c:917: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* | board/amcc/yucca/flash.c: Fix compile warningWolfgang Denk2009-09-15-3/+4
| | | | | | | | | | | | | | | | | | Fix warning: flash.c:919: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* | board/amcc/taihu/flash.c: Fix compile warningWolfgang Denk2009-09-15-6/+8
|/ | | | | | | | | | | | Fix warnings: flash.c: In function 'write_word_1': flash.c:696: warning: dereferencing type-punned pointer will break strict-aliasing rules flash.c: In function 'write_word_2': flash.c:1044: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix "chip_config" command for AMCC ArchesStefan Roese2009-08-18-16/+18
| | | | | | | | | | This patch fixes the "chip_config" command for I2C bootstrap EEPROM configuration. First it changes the I2C bootstrap EEPROM address to 0x54 as this is used on Arches (instead of 0x52 on Canyonlands/ Glacier). Additionally, the NAND bootstrap settings are removed for Arches since Arches doesn't support NAND-booting. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add support for PPC460EX/460GT rev B chip to AMCC CanyonlandsStefan Roese2009-07-30-9/+17
| | | | | | | This patch is based on a diff created by Phong Vo from AMCC. Signed-off-by: Phong Vo <pvo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix problem with NOR range assignment in Canyonlands ft_board_setupStefan Roese2009-07-28-15/+0
| | | | | | | | | | | This patch fixes the problem, that the current fdt board fixup code only set's one range, the one for NOR. By this it's overwriting the already correctly configured values done in __ft_board_setup(). Just remove this now unneeded NOR fixup and all the ranges are correctly defined. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Felix Radensky <felix@embedded-sol.com>
* ppc4xx: Add some NAND-booting bootstrap entries to Kilauea chip_config cmdStefan Roese2009-07-28-4/+20
| | | | | | | | | This patch adds some I2C bootstrap setting for NAND booting to the Kilauea chip_config command ("533-nand" and "600-nand"). Additionally some incorrectly indented lines are fixed. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix Arches DDR2 initializationStefan Roese2009-07-28-12/+18
| | | | | | | | | Testing on AMCC Arches with the latest U-Boot version yielded that DDR2 initialization is currently broken. U-Boot hangs upon relocation to SDRAM or crashes with random traps. This patch fixes this problem. Arches now uses a different WRDTR and CLKTR default setting than Canyonlands/Glacier. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add chip_config command to AMCC Kilauea eval boardStefan Roese2009-07-24-298/+76
| | | | | | | | This patch removes the "alterpll" command and replaces it with the now ppc4xx standard "chip_config" command to configure the I2C bootstrap EEPROM. Signed-off-by: Stefan Roese <sr@denx.de>
* Add "chip_config" command for PPC4xx bootstrap configurationStefan Roese2009-07-24-197/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a generic command for programming I2C bootstrap eeproms on PPC4xx. An implementation for Canyonlands board is included. The command name is intentionally chosen not to be PPC4xx specific. This way other CPU's/SoC's can implement a similar command under the same name, perhaps with a different syntax. Usage on Canyonlands: => chip_config Available configurations (I2C address 0x52): 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 600-nand - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100 800-nor - NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100 800-nand - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100 1000-nand - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100 1066-nor - NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88 *** 1066-nand - NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88 => chip_config 600-nor Using configuration: 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 done (dump via 'i2c md 52 0.1 10') Reset the board for the changes to take effect Other 4xx boards will be migrated to use this command soon as well. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Dirk Eibach <eibach@gdsys.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* ppc4xx: Fix FDT EBC mappings on CanyonlandsFelix Radensky2009-07-08-2/+4
| | | | | | | | | | This patch fixes 2 problems with FDT EBC mappings on Canyonlands. First, NAND EBC mapping was missing, making Linux NAND driver unusable on this board. Second, NOR remapping code assumed that NOR is always on CS0, however when booting from NAND NOR is on CS3. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* General help message cleanupWolfgang Denk2009-06-12-40/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many of the help messages were not really helpful; for example, many commands that take no arguments would not print a correct synopsis line, but "No additional help available." which is not exactly wrong, but not helpful either. Commit ``Make "usage" messages more helpful.'' changed this partially. But it also became clear that lots of "Usage" and "Help" messages (fields "usage" and "help" in struct cmd_tbl_s respective) were actually redundant. This patch cleans this up - for example: Before: => help dtt dtt - Digital Thermometer and Thermostat Usage: dtt - Read temperature from digital thermometer and thermostat. After: => help dtt dtt - Read temperature from Digital Thermometer and Thermostat Usage: dtt Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Add Sequoia RAM-booting targetStefan Roese2009-06-12-3/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds another build target for the AMCC Sequoia PPC440EPx eval board. This RAM-booting version is targeted for boards without NOR FLASH (NAND booting) which need a possibility to initially program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000) configured to setup the SDRAM, this debugger can load this RAM- booting image to the target address in SDRAM (in this case 0x1000000) and start it there. Then U-Boot's standard NAND commands can be used to program the NAND FLASH (e.g. "nand write ..."). Here the commands to load and start this image from the BDI2000: 440EPX>reset halt 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin 440EPX>go 0x1000000 Please note that this image automatically scans for an already initialized SDRAM TLB (detected by EPN=0). This TLB will not be cleared. This TLB doesn't need to be TLB #0, this RAM-booting version will detect it and preserve it. So booting via BDI2000 will work and booting with a complete different TLB init via U-Boot works as well. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove unused code for Sequoia NAND booting versionStefan Roese2009-04-16-5/+1
| | | | | | | | The current define of get_bus_freq() in the CONFIG_NAND_SPL #ifdef is not used at all. This patch changes it's define to the currently used value of 133333333 and removes the unnecessary code. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fixup chip-selects in dtb for NAND-booting SequoiaStefan Roese2009-04-16-2/+56
| | | | | | | | | | | | | | | | | | | | Currently the NOR & NAND support in Linux only works for the "standard" Sequoia, the version booting for NOR flash. The NAND-booting version has the chip-selects swapped. Here the chip-select mappings: "Standard" NOR-booting version: CS0 NOR CS3 NAND NAND-booting version: CS0 NAND CS3 NOR With this path the dtb gets fixed-up, so that the correct chip-select numbers are patched in the dtb enabling correct NOR & NAND support in Linux on the NAND-booting Sequoia version. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Sequoia: Fix TLB reassignment in NAND booting codeStefan Roese2009-03-26-1/+1
| | | | | | | | | | This patch fixes a bug in the Sequoia TLB init code to reconfigure the correct TLB (boot space) after running from RAM. This bug was introduced with patch 4d332dbeb08f5863d1ea69d91a00c5499d3a87ed [ppc4xx: Make Sequoia boot vxWorks] which changed the order of the TLB in the Sequoia init.S file. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix all linker script to handle all rodata sectionsTrent Piepho2009-03-20-66/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
* Fix AMCC Sequoia board DDR memory configurationMikhail Zolotaryov2009-03-17-1/+1
| | | | | | | | | | | | | | | Sequoia board schematics (DES0211_11_SCH_11.pdf, page 5, unit U1D) specifies that BankSel#1 is not connected, while bootloader memory configuration is (board/amcc/sequoia/sdram.c): mtsdram(DDR0_10, 0x00000300); i.e. both Chip Selects used - not correct. If we change to correct value here: mtsdram(DDR0_10, 0x00000100); memory is accessible OK also. Signed-off-by: Mikhail Zolotaryov <lebon@lebon.org.ua> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix problem with board_eth_init() vs cpu_eth_init() on AMCC boardsStefan Roese2009-02-12-0/+4
| | | | | | | | Some AMCC eval boards do have a board_eth_init() function calling pci_eth_init(). These boards need to call cpu_eth_init() explicitly now with the new eth_init rework. Signed-off-by: Stefan Roese <sr@denx.de>
* Command usage cleanupPeter Tyser2009-01-28-26/+26
| | | | | | | | Remove command name from all command "usage" fields and update common/command.c to display "name - usage" instead of just "usage". Also remove newlines from command usage fields. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* amcc: Clean up command usage outputPeter Tyser2009-01-28-9/+9
| | | | | | | Update taihu and taishan commands to use cmd_usage() function to display usage messages. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Standardize command usage messages with cmd_usage()Peter Tyser2009-01-28-12/+12
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initializationDave Mitchell2008-11-21-1/+1
| | | | | | | | | | | | | | | | | | Expanded OCM TLB to allow access to 64K OCM as well as 256K of internal SRAM. Adjusted internal SRAM initialization to match updated user manual recommendation. OCM & ISRAM are now mapped as follows: physical virtual size ISRAM 0x4_0000_0000 0xE300_0000 256k OCM 0x4_0004_0000 0xE304_0000 64k A single TLB was used for this mapping. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRsDave Mitchell2008-11-21-11/+12
| | | | | | | | | | | Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and L2 cache DCRs from ppc440.h to this new header. Also converted these DCR defines from lowercase to uppercase and modified referencing modules to use them. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Align end of bss by 4 bytesSelvamuthukumar2008-11-18-0/+22
| | | | | | | | | | Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Coding Style cleanup, update CHANGELOGWolfgang Denk2008-11-02-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-10-21-0/+169
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| * ppc4xx: Add 1.0 & 1.066 GHz to canyonlands bootstrap command for PLL setupStefan Roese2008-10-21-0/+12
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add AMCC Arches board support (dual 460GT)Adam Graham2008-10-21-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-20/+20
|/ | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-761/+761
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ppc4xx: Canyonlands: Remove unnecessary FDT warning upon DTB fixupStefan Roese2008-09-22-12/+4
| | | | | | | | | Depending on the configuration jumper "SATA SELECT", U-Boot disabled either one PCIe node or the SATA node in the device tree blob. This patch removes the unnecessary and even confusing warning, when the node is not found at all. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'Makefile-next' of git://git.denx.de/u-boot-armWolfgang Denk2008-09-12-55/+53
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| * rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-36/+36
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * move cmd_get_data_size to command.cJean-Christophe PLAGNIOL-VILLARD2008-09-10-2/+0
| | | | | | | | | | | | add CMD_DATA_SIZE macro to enable it Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASHJean-Christophe PLAGNIOL-VILLARD2008-09-10-12/+12
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * rename environment.c in env_embedded.c to reflect is functionalityJean-Christophe PLAGNIOL-VILLARD2008-09-10-6/+6
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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