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* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-109/+123
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| * ppc4xx: Update Sequoia NAND booting support with ECCStefan Roese2007-06-01-0/+4
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Prepare Bamboo port for NAND booting supportStefan Roese2007-06-01-109/+119
| | | | | | | | | | | | | | | | | | | | This patch updates the "normal" Bamboo NOR booting port, so that it is compatible with the coming soon NAND booting Bamboo port. It also enables the 2nd NAND flash on the Bamboo. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Undo Sequoia patch for dynamic EBC speed support of 83MHzStefan Roese2007-06-01-6/+0
| | | | | | | | | | | | | | | | This patch undoes the patch by Jeff Mann with commit-id ada4697d. As suggested by AMCC it is not recommended to dynamically change the EBC speed after bootup. So we undo this change to be on the safe side. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Update AMCC Acadia support for board revision 1.1Stefan Roese2007-05-24-1/+8
| | | | | | | | | | | | | | | | | | | | | | This patch updates the Acadia (405EZ) support for the new 1.1 board revision. It also adds support for NAND FLASH via the 4xx NDFC. Please note that the jumper J7 must be in position 2-3 for this NAND support. Position 1-2 is for NAND booting only. NAND booting support will follow later. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Run new sequoia boards with an EBC speed of 83MHzJeffrey Mann2007-05-16-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the Sequoia board does not boot with an EBC faster than 66MHz, the clock divider are changed after the initial boot process. This allows for maximum clocking speeds to be achieved on newer boards. Sequoia boards with 666.66 MHz processors require that the EBC divider be set to 3 in order to start the initial boot process at a slower EBC speed. After the initial boot process, the divider can be set back to 2, which will cause the boards to run at 83.333MHz. This is backward compatible with boards with 533.33 MHz processors, as these boards will already be set with an EBC divider of 2. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
* | ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND bootingStefan Roese2007-05-05-1/+9
|/ | | | | | | | Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big for the 4k NAND boot image so define bus_frequency to 133MHz here which is save for the refresh counter setup. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Bamboo: Use current NAND driver and *not* the legacy driverStefan Roese2007-04-29-94/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update Acadia to not setup PLL when booting via bootstrap EEPROMStefan Roese2007-04-18-3/+7
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change SysACE address on KatmaiStefan Roese2007-04-02-1/+1
| | | | | | | | With this new base address of the Xilinx SystemACE controller the Linux driver will be easier to adapt, since it can now be mapped via the "normal" ioremap() call. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-03-31-10/+12
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| * Code cleanup. Update CHANGELOGWolfgang Denk2007-03-21-22/+10
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* | ppc4xx: Update Katmai bootstrap commandStefan Roese2007-03-31-1/+3
| | | | | | | | | | | | | | Now the DDR2 frequency is also 2*PLB frequency when 166MHz PLB is selected. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix "bootstrap" command for Katmai boardStefan Roese2007-03-31-76/+25
| | | | | | | | | | | | | | | | The board specific "bootstrap" command is now fixed and can be used for the AMCC Katmai board to configure different CPU/PLB/OPB frequencies. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-24-1725/+73
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| * [PATCH] Add 4xx GPIO functionsStefan Roese2007-03-24-10/+2
| | | | | | | | | | | | | | This patch adds some 4xx GPIO functions. It also moves some of the common code and defines into a common 4xx GPIO header file. Signed-off-by: Stefan Roese <sr@denx.de>
| * [PATCH] Small Sequoia cleanupStefan Roese2007-03-24-2/+2
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * [PATCH] Clean up 40EZ/Acadia supportStefan Roese2007-03-24-1713/+69
| | | | | | | | | | | | | | This patch cleans up all the open issue of the preliminary Acadia support. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-21-0/+2257
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| * [PATCH] Add AMCC Acadia (405EZ) eval board supportStefan Roese2007-03-21-0/+2257
| | | | | | | | | | | | | | | | | | This patch adds support for the new AMCC Acadia eval board. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Use dynamic SDRAM TLB setup on AMCC Ebony eval boardStefan Roese2007-03-16-58/+19
| | | | | | | | | | | | | | | | Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix file mode of sequoia.cStefan Roese2007-03-08-0/+0
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Clear Sequoia/Rainier security engine reset bitsJohn Otken john@softadvances.com2007-03-08-0/+4
| | | | | | | | Signed-off-by: John Otken john@softadvances.com <john@softadvances.com>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-597/+94
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| * \ Merge with /home/stefan/git/u-boot/yucca-ddr2Stefan Roese2007-03-08-597/+94
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| | * | [PATCH] Update AMCC Luan 440SP eval board supportStefan Roese2007-03-08-226/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
| | * | [PATCH] Update AMCC Yucca 440SPe eval board supportStefan Roese2007-03-08-371/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Yucca now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Small AMCC Katmai 440SPe updateStefan Roese2007-03-08-0/+10
| | |/ | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-07-63/+19
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| * | [PATCH] Use dynamic SDRAM TLB setup on AMCC Ocotea eval boardStefan Roese2007-03-07-63/+19
| |/ | | | | | | | | | | | | | | Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the DDR memory are dynamically programmed matching the total size of the equipped memory (DIMM modules). Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setupStefan Roese2007-03-06-8/+13
|/ | | | | | | | | | | | | | As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update AMCC Katmai 440SPe eval board supportStefan Roese2007-03-01-75/+25
| | | | | | | | | | | This patch updates the recently added Katmai board support. The biggest change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2 driver. Please note, that still some problems are left with some memory configurations. See the driver for more details. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Clean up Katmai (440SPe) linker scriptStefan Roese2007-02-20-16/+0
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Add support for the AMCC Katmai (440SPe) eval boardStefan Roese2007-02-20-0/+1200
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/sr/git/u-boot/denx-merge-srWolfgang Denk2007-01-30-913/+8
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| * [PATCH] Merge Yosemite & Yellowstone board portsStefan Roese2007-01-30-913/+8
| | | | | | | | | | | | | | | | | | Now the AMCC eval boards Yosemite (440EP) and Yellowstone (440GR) share one config file and all board specific files. This way we don't have to maintain two different sets of files for nearly identical boards. Signed-off-by: Stefan Roese <sr@denx.de>
* | Minor code cleanup.Wolfgang Denk2007-01-19-4/+4
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* [PATCH] Add support for AMCC Taishan PPC440GX eval boardStefan Roese2007-01-18-0/+1374
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/hs/SC3/u-bootWolfgang Denk2007-01-15-3/+0
|\ | | | | | | Some code cleanup.
* | [PATCH] Update Yellowstone (440GR) to display board rev and PCI bus speedStefan Roese2007-01-13-18/+7
| | | | | | | | | | | | | | | | | | | | Now the board revision and the current PCI bus speed are printed after the board message. Also the EBC initialising is now done via defines in the board config file. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Update Yosemite (440EP) to display board rev and PCI bus speedStefan Roese2007-01-13-18/+7
| | | | | | | | | | | | | | | | | | | | Now the board revision and the current PCI bus speed are printed after the board message. Also the EBC initialising is now done via defines in the board config file. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Update Sequoia (440EPx) to display board rev and PCI bus speedStefan Roese2007-01-13-0/+7
| | | | | | | | | | | | | | Now the board revision and the current PCI bus speed are printed after the board message. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx)Stefan Roese2007-01-05-3/+12
| | | | | | | | | | | | | | This fix will make the MAL burst disabling patch for the Linux EMAC driver obsolete. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese2007-01-05-10/+866
|/ | | | | | | | | | This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Fix sequoia flash autodetection (finally correct)Stefan Roese2006-12-22-3/+11
| | | | | | | Now 32MByte and 64MByte FLASH is know to work and other configurations should work too. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/denxStefan Roese2006-11-10-83/+77
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| * Fix sequoia separate object direcory building problems.Marian Balakowicz2006-10-23-2/+1
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| * Move "ar" flags to config.mk to allow for silent "make -s"Wolfgang Denk2006-10-09-10/+10
| | | | | | | | Based on patch by Mike Frysinger, 20 Jun 2006
| * Coding style cleanupWolfgang Denk2006-10-09-39/+36
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| * Fix TLB setup for Ocotea boardStefan Roese2006-10-04-26/+30
| | | | | | | | Patch by Stefan Roese, 30 Sep 2006
generated by cgit v1.1 at 2024-11-27 01:02:36 +0000