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* SPI API improvementsHaavard Skinnemoen2008-06-03-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gets rid of the spi_chipsel table and adds a handful of new functions that makes the SPI layer cleaner and more flexible. Instead of the spi_chipsel table, each board that wants to use SPI gets to implement three hooks: * spi_cs_activate(): Activates the chipselect for a given slave * spi_cs_deactivate(): Deactivates the chipselect for a given slave * spi_cs_is_valid(): Determines if the given bus/chipselect combination can be activated. Not all drivers may need those extra functions however. If that's the case, the board code may just leave them out (assuming they know what the driver needs) or rely on the linker to strip them out (assuming --gc-sections is being used.) To set up communication parameters for a given slave, the driver needs to call spi_setup_slave(). This returns a pointer to an opaque spi_slave struct which must be passed as a parameter to subsequent SPI calls. This struct can be freed by calling spi_free_slave(), but most driver probably don't want to do this. Before starting one or more SPI transfers, the driver must call spi_claim_bus() to gain exclusive access to the SPI bus and initialize the hardware. When all transfers are done, the driver must call spi_release_bus() to make the bus available to others, and possibly shut down the SPI controller hardware. spi_xfer() behaves mostly the same as before, but it now takes a spi_slave parameter instead of a spi_chipsel function pointer. It also got a new parameter, flags, which is used to specify chip select behaviour. This may be extended with other flags in the future. This patch has been build-tested on all powerpc and arm boards involved. I have not tested NIOS since I don't have a toolchain for it installed, so I expect some breakage there even though I've tried fixing up everything I could find by visual inspection. I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and DataFlash drivers posted as a follow-up. I'd like some help testing other boards that use the existing SPI API. But most of all, I'd like some comments on the new API. Is this stuff usable for everyone? If not, why? Changed in v4: - Build fixes for various boards, drivers and commands - Provide common struct spi_slave definition that can be extended by drivers - Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate - Make default bus and mode build-time configurable - Override default SPI bus ID and mode on mx32ads and imx31_litekit. Changed in v3: - Add opaque struct spi_slave for controller-specific data associated with a slave. - Add spi_claim_bus() and spi_release_bus() - Add spi_free_slave() - spi_setup() is now called spi_setup_slave() and returns a struct spi_slave - soft_spi now supports four SPI modes (CPOL|CPHA) - Add bus parameter to spi_setup_slave() - Convert the new i.MX32 SPI driver - Convert the new MC13783 RTC driver Changed in v2: - Convert the mpc8xxx_spi driver and the mpc8349emds board to the new API. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Tested-by: Guennadi Liakhovetski <lg@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-195/+195
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Canyonlands: Disable PCIe0/SATA in dev-tree depending on selectionStefan Roese2008-05-19-1/+30
| | | | | | | | | | | | | | | When SATA is selected (via jumper J6) we need to disable the first PCIe node in the device tree, so that Linux doesn't initialize it. Otherwise the Linux SATA driver will fail to detect the devices. The same goes the other way around too. So if PCIe is selected we need to disable the SATA node in the device tree. This is because PCIe port 0 and SATA on 460EX share the same pins (multiplexed) and we have to configure in U-Boot which peripheral is enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix bogus Canyonlands config.mkStefan Roese2008-05-14-9/+1
| | | | | | | This patch fixes the canyonlands config.mk file to enable correct out-of-tree builds. Thanks to Wolfgang Denk for spotting this. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add 405EX(r) revision C PVR definitions and detection codeStefan Roese2008-05-13-7/+12
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: acadia: Add fdt support and fix section overlap problemStefan Roese2008-05-08-1/+1
| | | | | | | | | | | | | This patch adds fdt (flattened device tree) support to the AMCC Acadia eval board. This increases the image size and it doesn't fit anymore into 256kByte. Since we didn't want to remove features from the configuration, we decided to increase the U-Boot image size (add one flash sector). Also changed the default environment definition to make it independent of such changes. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add device tree support to AMCC YosemiteIra Snyder2008-05-08-0/+23
| | | | | | | | | Add support for booting with a device tree blob. This is needed to boot ARCH=powerpc kernels. Also add support for setting the eth0 mac address via the ethaddr variable. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Stefan Roese <sr@denx.de>
* katmai: fix section overlap problemWolfgang Denk2008-04-28-1/+1
| | | | | | | | | | | Since we didn't want to remove features from the configuration, we decided to increase the U-Boot image size (add one flash sector). Also changed the default environment definition to make it independent of such changes. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change Canyonlands to support booting from 2k page NAND devicesStefan Roese2008-04-18-2/+16
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Remove all the search paths from the .lds files.Jason Wessel2008-04-17-21/+0
| | | | | | | The cross compiler is responsible for providing the correct libraries and the logic to find the linking libraries. Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
* ppc4xx: Canyonlands: Init SATA/PCIe port correctlyStefan Roese2008-04-02-12/+34
| | | | | | | | | Canyonlands (460EX) shares the first PCIe interface with the SoC SATA interface. This usage can be configured with the jumper J6. This patch correctly configures the SATA/PCIe PHY for SATA usage when this jumper is installed. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Canyonlands: Print SATA/PCIe configuration and board revisionStefan Roese2008-03-28-3/+39
| | | | | | | | | Canyonlands (460EX) shares the first PCIe interface with the SoC SATA interface. This usage can be configured with the jumper J6. This patch displays the current configuration upon bootup and changes the PCIe init loop, to only initialize the availabel PCIe slots. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix Canyonlands linker script (remove bogus ASSERT)Stefan Roese2008-03-27-2/+0
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Correctly pass phyiscal FLASH base address into dtbStefan Roese2008-03-27-1/+1
| | | | | | | | | The routine ft_board_setup() configures the EBC NOR mappings for the Linux physmap_of driver. Since on 460EX/GT we remap the FLASH from 0x4.fc00.0000 to 0x4.cc00.0000 because of the max. 16MByte boot-CS problem, we need to pass the corrected address here too. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add AMCC Glacier 406GT eval board supportStefan Roese2008-03-27-9/+16
| | | | | | | | | | | | | | This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval boardStefan Roese2008-03-15-0/+17
| | | | | | | This patch adds USB OHCI support to the Canyonlands board port. It also enables EXT2 support. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add Canyonlands NAND booting supportStefan Roese2008-03-15-17/+179
| | | | | | | | | | | | | | | 460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add AMCC Canyonlands support (460EX) (1/3)Stefan Roese2008-03-15-0/+915
| | | | | | | This patch adds support for the AMCC Canyonlands 460EX evaluation board. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix comment in 405EX DDR2 init codeStefan Roese2008-03-15-4/+4
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* fix taihu soft spi_readMarkus Brunner2008-03-07-1/+1
| | | | | | | The taihu board used gpio_read_out_bit which reads the output register and not the pin state. Signed-off-by: Markus Brunner <super.firetwister@gmail.com>
* ppc4xx: Fix acadia_nand build problemStefan Roese2008-02-25-0/+2
| | | | | | | Don't include testdram() on NAND-booting target acadia_nand. This saves a few bytes and makes the target build clean again. Signed-off-by: Stefan Roese <sr@denx.de>
* PPC440EPx: Optionally enable second I2C busMike Nuss2008-02-16-1/+4
| | | | | | | | | The option CONFIG_I2C_MULTI_BUS does not have any effect on Sequoia, the PPC440EPx reference platform, because IIC1 is never enabled. Add Sequoia board code to turn on IIC1 if CONFIG_I2C_MULTI_BUS is selected. Signed-off-by: Mike Nuss <mike@terascala.com> Cc: Stefan Roese <sr@denx.de>
* Coding Style Cleanup; update CHANGELOGWolfgang Denk2008-01-23-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Fix remaining CONFIG_COMMANDS in 4xx filesStefan Roese2008-01-17-2/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Sequoia coding style cleanup and beautificationMatthias Fuchs2008-01-16-139/+114
| | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: Update Kilauea CPLD configuration with USB PHY reset bitStefan Roese2008-01-14-7/+7
| | | | | | | | | Now that bit 29 is the USB PHY reset bit, update the Kilauea port to remove the USB PHY reset after powerup. The CPLD will keep the USB PHY in reset (active low) until the bit is set to 1 in board_early_init_f(). Signed-off-by: Stefan Roese <sr@denx.de>
* Makalu: fix compile warningWolfgang Denk2008-01-13-0/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Fix linker scripts: add NOLOAD atribute to .bss/.sbss sectionsWolfgang Denk2008-01-12-19/+19
| | | | | | | | | | | | | | | | | | | With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Fix sdram init on Sequoia boardsStefan Roese2008-01-11-0/+7
| | | | | | | | Clear possible errors in MCSR resulting from data-eye-search. If not done, then we could get an interrupt later on when exceptions are enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make Sequoia boot vxWorksNiklaus Giger2008-01-10-12/+14
| | | | | | | | | | | | | | vxWorks expects in TLB 0 a entry for the Machine Check interrupt TLB 1 a entry for the RAM TLB 2 a entry for the EBC TLB 3 a entry for the boot flash After changing the baudrate to 9600 I had no problems to boot the vxWorks image as distributed by WindRiver (Revision 2.0/1 from June 18, 2007) Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* ppc4xx: assign PCI interrupts on seuqoia boardsMatthias Fuchs2008-01-09-0/+14
| | | | | | Some operating systems rely on assigned PCI interrupts. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* Merge branch 'katmai-ddr-gda'Stefan Roese2008-01-05-1/+13
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| * ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setupStefan Roese2008-01-05-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On Katmai the complete auto-calibration somehow doesn't seem to produce the best results, meaning optimal values for RQFD/RFFD. This was discovered by GDA using a high bandwidth scope, analyzing the DDR2 signals. GDA provided a fixed value for RQFD, so now on Katmai "only" RFFD is auto-calibrated. This patch also adds RDCC calibration as mentioned on page 7 of the AMCC PowerPC440SP/SPe DDR2 application note: "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia boardLawrence R. Johnson2008-01-04-30/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Note: this patch changes the configuration of some GPIO registers: Register Old Value New Value --------------- ---------- ---------- DCR GPIO0_TCR 0x0000000F 0x0000F0CF DCR GPIO0_TSRH 0x55005000 0x00000000 DCR GPIO1_TCR 0xC2000000 0xE2000000 DCR GPIO1_TSRL 0x0C000000 0x00200000 DCR GPIO1_ISR2L 0x00050000 0x00110000 Signed-off-by: Larry Johnson <lrj@acm.org>
* | PPC4xx: Remove sdram.h from board/amcc/sequoiaLarry Johnson2008-01-04-505/+0
| | | | | | | | | | | | These definitions are now in "include/ppc440.h". Signed-off-by: Larry Johnson <lrj@acm.org>
* | PPC4xx: Use common code for Sequoia board SDRAM supportLarry Johnson2008-01-04-338/+6
|/ | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* Add definitions for 440EPx/GRx SDRAM controller to ppc440.hLarry Johnson2007-12-27-2/+2
| | | | | | | | | This patch adds the Denali SDRAM controller definitions to "ppc440.h". It also fixes two typos in the definitions, so the board-specific "sdram.h" files containing these definitions are also fixed to avoid compiler warnings. Signed-off-by: Larry Johnson <lrj@acm.org>
* Use out_be32() and friends to access memory-mapped registers in sequoia.cLarry Johnson2007-12-27-29/+29
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* Use definitions from "asm-ppc/mmu.h" in init.S for SequoiaLarry Johnson2007-12-27-49/+1
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Add fdt support to AMCC Katmai eval boardStefan Roese2007-12-27-0/+23
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Bring 4xx fdt support up-to-dateStefan Roese2007-12-27-1/+25
| | | | | | | | This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 405EX: Correctly enable USB pinsStefan Roese2007-12-08-0/+16
| | | | | | | | This patch selects the USB data pins in the 405EX GPIO and MFC (multi function control) registers. This is done for the AMCC Kilauea and Makalu eval boards. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable hardware-fix for PCI/DMA errata on AMCC 440SP/SPe boardsStefan Roese2007-12-06-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the hardware-fix for the PCI/DMA errata's 19+22 by setting the FIXD bit in the SDR0_MFR register. Here a description of the symptoms: Problem Description ------------------------------ If a DMA is performed between memory and PCI with the DMA 1 Controller using prefetch, and as a result uses a special purpose buffer selected by the PCIXn Bridge Options 1 Register (PCIXn_BRDGOPT1[RBP7] - bits 31-29), the first part of the transfer sequence is performed twice. The PPC440SPe PCI Controller requests more data than was needed such that in the case of enforce memory protection, a host CPU exception can occur. No data is corrupted, because data transfer is stopped in the PCI Controller. Prefetch enable is specified by setting DMA Configuration Register (I2O0_DMAx_CFG[DXEPD] - bit 31) to 0. Behavior that may be observed in a running system --------------------------------------------------------------------------- 1. DMA performance is decreased because of the double access on the PCI bus interface. 2. If an illegal access to some address on the PCI bus is detected at the system level, a machine check or similar system error may occur. Workarounds Available ---------------------------------- 1. Do not program prefetch. Note that a prefetch command cannot be programmed without selecting a special purpose buffer. 2. To avoid crossing a physical boundary of the PCI slave device, add 512 bytes of address to the PCI address range. This patch was originally provided by Pravin M. Bathija <pbathija@amcc.com> from AMCC and slighly changed. Signed-off-by: Pravin M. Bathija <pbathija@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Kilauea: Add PCIe reset assertion upon power-upStefan Roese2007-11-30-9/+6
| | | | | | | | This manual PCIe reset triggering solves the problem seen with the Intel EPRO/1000 card, which was not detected (link not established) upon power-up reset. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update AMCC Makalu for board rev 1.1Stefan Roese2007-11-16-54/+13
| | | | | | | | | | | This patch adds changes needed for Makalu rev 1.1: - Enable 2nd DDR2 bank resulting in 256MByte of SDRAM - Enable 2nd ethernet port EMAC1 - Use generic GPIO configuration framework (CFG_4xx_GPIO_TABLE) - Reset PCIe ports via GPIO upon bootup Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Small AMCC Kilauea cleanupStefan Roese2007-11-15-39/+0
| | | | | | Remove not needed pci_target_init() function. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make output a little shorter on PCIe detectionStefan Roese2007-11-05-17/+12
| | | | | | Now not max 3 lines but 2 lines are printed per PCIe port. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add AMCC Kilauea/Haleakala NAND booting supportStefan Roese2007-11-03-1/+148
| | | | | | | This patch adds NAND booting support for the AMCC 405EX(r) eval boards. Again, only one image supports both targets. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAMStefan Roese2007-10-31-0/+4
| | | | | | | | | | | | | | This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board supportStefan Roese2007-10-31-3/+33
| | | | | | | | | | The Haleakala is nearly identical with the Kilauea eval board. The only difference is that the 405EXr only supports one EMAC and one PCIe interface. This patch adds support for the Haleakala board by using the identical image for Kilauea and Haleakala. The distinction is done by comparing the PVR. Signed-off-by: Stefan Roese <sr@denx.de>
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