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* PPC440EPx: Optionally enable second I2C busMike Nuss2008-02-16-1/+4
| | | | | | | | | The option CONFIG_I2C_MULTI_BUS does not have any effect on Sequoia, the PPC440EPx reference platform, because IIC1 is never enabled. Add Sequoia board code to turn on IIC1 if CONFIG_I2C_MULTI_BUS is selected. Signed-off-by: Mike Nuss <mike@terascala.com> Cc: Stefan Roese <sr@denx.de>
* Coding Style Cleanup; update CHANGELOGWolfgang Denk2008-01-23-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Sequoia coding style cleanup and beautificationMatthias Fuchs2008-01-16-139/+114
| | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* Fix linker scripts: add NOLOAD atribute to .bss/.sbss sectionsWolfgang Denk2008-01-12-2/+2
| | | | | | | | | | | | | | | | | | | With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Fix sdram init on Sequoia boardsStefan Roese2008-01-11-0/+7
| | | | | | | | Clear possible errors in MCSR resulting from data-eye-search. If not done, then we could get an interrupt later on when exceptions are enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make Sequoia boot vxWorksNiklaus Giger2008-01-10-12/+14
| | | | | | | | | | | | | | vxWorks expects in TLB 0 a entry for the Machine Check interrupt TLB 1 a entry for the RAM TLB 2 a entry for the EBC TLB 3 a entry for the boot flash After changing the baudrate to 9600 I had no problems to boot the vxWorks image as distributed by WindRiver (Revision 2.0/1 from June 18, 2007) Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* ppc4xx: assign PCI interrupts on seuqoia boardsMatthias Fuchs2008-01-09-0/+14
| | | | | | Some operating systems rely on assigned PCI interrupts. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia boardLawrence R. Johnson2008-01-04-30/+1
| | | | | | | | | | | | | | Note: this patch changes the configuration of some GPIO registers: Register Old Value New Value --------------- ---------- ---------- DCR GPIO0_TCR 0x0000000F 0x0000F0CF DCR GPIO0_TSRH 0x55005000 0x00000000 DCR GPIO1_TCR 0xC2000000 0xE2000000 DCR GPIO1_TSRL 0x0C000000 0x00200000 DCR GPIO1_ISR2L 0x00050000 0x00110000 Signed-off-by: Larry Johnson <lrj@acm.org>
* PPC4xx: Remove sdram.h from board/amcc/sequoiaLarry Johnson2008-01-04-505/+0
| | | | | | These definitions are now in "include/ppc440.h". Signed-off-by: Larry Johnson <lrj@acm.org>
* PPC4xx: Use common code for Sequoia board SDRAM supportLarry Johnson2008-01-04-338/+6
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* Add definitions for 440EPx/GRx SDRAM controller to ppc440.hLarry Johnson2007-12-27-2/+2
| | | | | | | | | This patch adds the Denali SDRAM controller definitions to "ppc440.h". It also fixes two typos in the definitions, so the board-specific "sdram.h" files containing these definitions are also fixed to avoid compiler warnings. Signed-off-by: Larry Johnson <lrj@acm.org>
* Use out_be32() and friends to access memory-mapped registers in sequoia.cLarry Johnson2007-12-27-29/+29
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* Use definitions from "asm-ppc/mmu.h" in init.S for SequoiaLarry Johnson2007-12-27-49/+1
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Bring 4xx fdt support up-to-dateStefan Roese2007-12-27-1/+24
| | | | | | | | This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAMStefan Roese2007-10-31-0/+4
| | | | | | | | | | | | | | This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap commandStefan Roese2007-10-18-1/+7
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix bug in I2C bootstrap values for Sequoia/RainierStefan Roese2007-10-15-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C bootstrap values that can be setup via the "bootstrap" command, were setup incorrect regarding the generation of the internal sync PCI clock. The values for PLB clock == 133MHz were slighly incorrect and the values for PLB clock == 166MHz were totally incorrect. This could lead to a hangup upon booting while PCI configuration scan. This patch fixes this issue and configures valid PCI divisor values for the sync PCI clock, with respect to the provided external async PCI frequency. Here the values of the formula in the chapter 14.2 "PCI clocking" from the 440EPx users manual: AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz 33MHz async PCI frequency: PLB = 133: => 32 <= 44.3 <= 65 (div = 3) PLB = 166: => 32 <= 55.3 <= 65 (div = 3) 66MHz async PCI frequency: PLB = 133: => 65 <= 66.5 <= 132 (div = 2) PLB = 166: => 65 <= 83 <= 132 (div = 2) Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & YosemiteStefan Roese2007-10-15-3/+4
| | | | | | | | | | | The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx SequoiaGary Jennejohn2007-08-31-0/+3
| | | | | | | | | | | | | | | | | | | | | The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese <sr@denx.de>. o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update Sequoia/Rainier bootstrap commandStefan Roese2007-08-16-48/+157
| | | | | | | As suggested by David Mitchell, here an update for the Sequoia/Rainier bootstrap command. Signed-off-by: Stefan Roese <sr@denx.de>
* resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPXNiklaus Giger2007-07-04-72/+4
| | | | Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-06-25-0/+10
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| * Extend POST support for PPC440Igor Lisitsin2007-06-22-0/+10
| | | | | | | | | | | | | | Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
* | ppc4xx: Add pci_pre_init() for 405 boardsStefan Roese2007-06-25-15/+2
|/ | | | | | | | This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add bootstrap command for AMCC Sequoia (440EPx) eval boardStefan Roese2007-06-19-1/+112
| | | | | | | | | | | This patch adds a board command to configure the I2C bootstrap EEPROM values. Right now 533 and 667MHz are supported for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 533 nor ;to configure the board for 533MHz NOR booting => bootstrap 667 nand ;to configure the board for 667MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-0/+4
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| * ppc4xx: Update Sequoia NAND booting support with ECCStefan Roese2007-06-01-0/+4
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Undo Sequoia patch for dynamic EBC speed support of 83MHzStefan Roese2007-06-01-6/+0
| | | | | | | | | | | | | | | | This patch undoes the patch by Jeff Mann with commit-id ada4697d. As suggested by AMCC it is not recommended to dynamically change the EBC speed after bootup. So we undo this change to be on the safe side. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Run new sequoia boards with an EBC speed of 83MHzJeffrey Mann2007-05-16-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because the Sequoia board does not boot with an EBC faster than 66MHz, the clock divider are changed after the initial boot process. This allows for maximum clocking speeds to be achieved on newer boards. Sequoia boards with 666.66 MHz processors require that the EBC divider be set to 3 in order to start the initial boot process at a slower EBC speed. After the initial boot process, the divider can be set back to 2, which will cause the boards to run at 83.333MHz. This is backward compatible with boards with 533.33 MHz processors, as these boards will already be set with an EBC divider of 2. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
* | ppc4xx: Sequoia: Remove cpu/ppc4xx/speed.c from NAND bootingStefan Roese2007-05-05-1/+9
|/ | | | | | | | Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big for the 4k NAND boot image so define bus_frequency to 133MHz here which is save for the refresh counter setup. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-24-2/+2
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| * [PATCH] Small Sequoia cleanupStefan Roese2007-03-24-2/+2
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix file mode of sequoia.cStefan Roese2007-03-08-0/+0
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Clear Sequoia/Rainier security engine reset bitsJohn Otken john@softadvances.com2007-03-08-0/+4
| | | | | | | | Signed-off-by: John Otken john@softadvances.com <john@softadvances.com>
* | [PATCH] Speed optimization of AMCC Sequoia/Rainier DDR2 setupStefan Roese2007-03-06-8/+13
|/ | | | | | | | | | | | | | As provided by the AMCC applications team, this patch optimizes the DDR2 setup for 166MHz bus speed. The values provided are also save to use on a "normal" 133MHz PLB bus system. Only the refresh counter setup has to be adjusted as done in this patch. For this the NAND booting version had to include the "speed.c" file from the cpu/ppc4xx directory. With this addition the NAND SPL image will just fit into the 4kbytes of program space. gcc version 4.x as provided with ELDK 4.x is needed to generate this optimized code. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/hs/SC3/u-bootWolfgang Denk2007-01-15-3/+0
|\ | | | | | | Some code cleanup.
* | [PATCH] Update Sequoia (440EPx) to display board rev and PCI bus speedStefan Roese2007-01-13-0/+7
| | | | | | | | | | | | | | Now the board revision and the current PCI bus speed are printed after the board message. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Clear PLB4A0_ACR[WRP] on Sequoia (440EPx)Stefan Roese2007-01-05-3/+12
| | | | | | | | | | | | | | This fix will make the MAL burst disabling patch for the Linux EMAC driver obsolete. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese2007-01-05-10/+866
|/ | | | | | | | | | This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Fix sequoia flash autodetection (finally correct)Stefan Roese2006-12-22-3/+11
| | | | | | | Now 32MByte and 64MByte FLASH is know to work and other configurations should work too. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix sequoia separate object direcory building problems.Marian Balakowicz2006-10-23-2/+1
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* Move "ar" flags to config.mk to allow for silent "make -s"Wolfgang Denk2006-10-09-1/+1
| | | | Based on patch by Mike Frysinger, 20 Jun 2006
* Coding style cleanupWolfgang Denk2006-10-09-36/+36
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* Fix reset problem in sequoia sdram init codeStefan Roese2006-10-04-6/+0
| | | | Patch by Stefan Roese, 23 Sep 2006
* Add support for AMCC Rainier PPX440GRx eval boardStefan Roese2006-09-13-0/+8
| | | | Patch by Stefan Roese, 13 Sep 2006
* Add NAND environment support for PPC440EPx Sequoia NAND boot configStefan Roese2006-09-12-1/+7
| | | | Patch by Stefan Roese, 12 Sep 2006
* Add support for AMCC Sequoia PPC440EPx eval boardStefan Roese2006-09-07-0/+1228
- Add support for PPC440EPx & PPC440GRx - Add support for PPC440EP(x)/GR(x) NAND controller in cpu/ppc4xx directory - Add NAND boot functionality for Sequoia board, please see doc/README.nand-boot-ppc440 for details - This Sequoia NAND image doesn't support environment in NAND for now. This will be added in a short while. Patch by Stefan Roese, 07 Sep 2006
generated by cgit v1.1 at 2024-11-20 16:26:35 +0000