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* ppc4xx: Sequoia: Fix TLB reassignment in NAND booting codeStefan Roese2009-03-26-1/+1
| | | | | | | | | | This patch fixes a bug in the Sequoia TLB init code to reconfigure the correct TLB (boot space) after running from RAM. This bug was introduced with patch 4d332dbeb08f5863d1ea69d91a00c5499d3a87ed [ppc4xx: Make Sequoia boot vxWorks] which changed the order of the TLB in the Sequoia init.S file. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix all linker script to handle all rodata sectionsTrent Piepho2009-03-20-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent gcc added a new unaligned rodata section called '.rodata.str1.1', which needs to be added the the linker script. Instead of just adding this one section, we use a wildcard ".rodata*" to get all rodata linker section gcc has now and might add in the future. However, '*(.rodata*)' by itself will result in sub-optimal section ordering. The sections will be sorted by object file, which causes extra padding between the unaligned rodata.str.1.1 of one object file and the aligned rodata of the next object file. This is easy to fix by using the SORT_BY_ALIGNMENT command. This patch has not be tested one most of the boards modified. Some boards have a linker script that looks something like this: *(.text) . = ALIGN(16); *(.rodata) *(.rodata.str1.4) *(.eh_frame) I change this to: *(.text) . = ALIGN(16); *(.eh_frame) *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) This means the start of rodata will no longer be 16 bytes aligned. However, the boundary between text and rodata/eh_frame is still aligned to 16 bytes, which is what I think the real purpose of the ALIGN call is. Signed-off-by: Trent Piepho <xyzzy@speakeasy.org>
* Fix AMCC Sequoia board DDR memory configurationMikhail Zolotaryov2009-03-17-1/+1
| | | | | | | | | | | | | | | Sequoia board schematics (DES0211_11_SCH_11.pdf, page 5, unit U1D) specifies that BankSel#1 is not connected, while bootloader memory configuration is (board/amcc/sequoia/sdram.c): mtsdram(DDR0_10, 0x00000300); i.e. both Chip Selects used - not correct. If we change to correct value here: mtsdram(DDR0_10, 0x00000100); memory is accessible OK also. Signed-off-by: Mikhail Zolotaryov <lebon@lebon.org.ua> Signed-off-by: Stefan Roese <sr@denx.de>
* Command usage cleanupPeter Tyser2009-01-28-1/+1
| | | | | | | | Remove command name from all command "usage" fields and update common/command.c to display "name - usage" instead of just "usage". Also remove newlines from command usage fields. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Standardize command usage messages with cmd_usage()Peter Tyser2009-01-28-1/+1
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Align end of bss by 4 bytesSelvamuthukumar2008-11-18-0/+2
| | | | | | | | | | Most of the bss initialization loop increments 4 bytes at a time. And the loop end is checked for an 'equal' condition. Make the bss end address aligned by 4, so that the loop will end as expected. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-39/+39
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV macros to CONFIG_ENVJean-Christophe PLAGNIOL-VILLARD2008-09-10-2/+2
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename CFG_ENV_IS_IN_FLASH in CONFIG_ENV_IS_IN_FLASHJean-Christophe PLAGNIOL-VILLARD2008-09-10-1/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* rename environment.c in env_embedded.c to reflect is functionalityJean-Christophe PLAGNIOL-VILLARD2008-09-10-1/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-08-12-0/+5
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| * ppc4xx: Sequoia has two UARTs in "4-pin" mode. Configure the GPIOs as per ↵Steven A. Falco2008-08-07-0/+5
| | | | | | | | | | | | | | | | | | | | | | schematic. The Sequoia board has two UARTs in "4-pin" mode. This patch modifies the GPIO configuration to match the schematic, and also sets the SDR0_PFC1 register to select the corresponding mode for the UARTs. Signed-off-by: Steven A. Falco <sfalco@harris.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boardsStefan Roese2008-07-13-21/+0
| | | | | | | | | | | | | | | | | | This patch removes some ft_board_setup() functions from some 4xx boards. This can be done since we now have a default weak implementation for this in cpu/ppc4xx/fdt.c. Only board in need for a different/custom implementation like canyonlands need their own version. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate PPC4xx UIC definesStefan Roese2008-07-11-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This 2nd patch now removes all UIC mask bit definition. They should be generated from the vectors by using the UIC_MASK() macro from now on. This way only the vectors need to get defined for new PPC's. Also only the really used interrupt vectors are now defined. This makes definitions for new PPC versions easier and less error prone. Another part of this patch is that the 4xx emac driver got a little cleanup, since now the usage of the interrupts is clearer. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate PPC4xx UIC definesStefan Roese2008-07-11-2/+1
| | | | | | | | | | | | | | | | | | This patch is the first step to consolidate the UIC related defines in the 4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next steps. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boardsStefan Roese2008-07-11-21/+0
|/ | | | | | | | | This patch removes some ft_board_setup() functions from some 4xx boards. This can be done since we now have a default weak implementation for this in cpu/ppc4xx/fdt.c. Only board in need for a different/custom implementation like canyonlands need their own version. Signed-off-by: Stefan Roese <sr@denx.de>
* Cleanup out-or-tree building for some boards (.depend)Wolfgang Denk2008-07-02-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-12-1/+1
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* ppc4xx: Unify AMCC's board config files (part 3/3)Stefan Roese2008-06-06-0/+4
| | | | | | | | | | | | | | | This patch series unifies the AMCC eval board ports by introducing a common include header for all AMCC eval boards: include/configs/amcc-common.h This header now includes all common configuration options/defines which are removed from the board specific headers. The reason for this is ease of maintenance and unified look and feel of all AMCC boards. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove implementations of testdram()Stefan Roese2008-06-03-38/+0
| | | | | | | This patch removes the used testdram() implementations of the board that are maintained by myself. Signed-off-by: Stefan Roese <sr@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-8/+8
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Remove all the search paths from the .lds files.Jason Wessel2008-04-17-2/+0
| | | | | | | The cross compiler is responsible for providing the correct libraries and the logic to find the linking libraries. Signed-off-by: Jason Wessel <jason.wessel@windriver.com>
* PPC440EPx: Optionally enable second I2C busMike Nuss2008-02-16-1/+4
| | | | | | | | | The option CONFIG_I2C_MULTI_BUS does not have any effect on Sequoia, the PPC440EPx reference platform, because IIC1 is never enabled. Add Sequoia board code to turn on IIC1 if CONFIG_I2C_MULTI_BUS is selected. Signed-off-by: Mike Nuss <mike@terascala.com> Cc: Stefan Roese <sr@denx.de>
* Coding Style Cleanup; update CHANGELOGWolfgang Denk2008-01-23-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Sequoia coding style cleanup and beautificationMatthias Fuchs2008-01-16-139/+114
| | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* Fix linker scripts: add NOLOAD atribute to .bss/.sbss sectionsWolfgang Denk2008-01-12-2/+2
| | | | | | | | | | | | | | | | | | | With recent toolchain versions, some boards would not build because or errors like this one (here for ocotea board when building with ELDK 4.2 beta): ppc_4xx-ld: section .bootpg [fffff000 -> fffff23b] overlaps section .bss [fffee900 -> fffff8ab] For many boards, the .bss section is big enough that it wraps around at the end of the address space (0xFFFFFFFF), so the problem will not be visible unless you use a 64 bit tool chain for development. On some boards however, changes to the code size (due to different optimizations) we bail out with section overlaps like above. The fix is to add the NOLOAD attribute to the .bss and .sbss sections, telling the linker that .bss does not consume any space in the image. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Fix sdram init on Sequoia boardsStefan Roese2008-01-11-0/+7
| | | | | | | | Clear possible errors in MCSR resulting from data-eye-search. If not done, then we could get an interrupt later on when exceptions are enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make Sequoia boot vxWorksNiklaus Giger2008-01-10-12/+14
| | | | | | | | | | | | | | vxWorks expects in TLB 0 a entry for the Machine Check interrupt TLB 1 a entry for the RAM TLB 2 a entry for the EBC TLB 3 a entry for the boot flash After changing the baudrate to 9600 I had no problems to boot the vxWorks image as distributed by WindRiver (Revision 2.0/1 from June 18, 2007) Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* ppc4xx: assign PCI interrupts on seuqoia boardsMatthias Fuchs2008-01-09-0/+14
| | | | | | Some operating systems rely on assigned PCI interrupts. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: Use CFG_4xx_GPIO_TABLE to configure Sequoia boardLawrence R. Johnson2008-01-04-30/+1
| | | | | | | | | | | | | | Note: this patch changes the configuration of some GPIO registers: Register Old Value New Value --------------- ---------- ---------- DCR GPIO0_TCR 0x0000000F 0x0000F0CF DCR GPIO0_TSRH 0x55005000 0x00000000 DCR GPIO1_TCR 0xC2000000 0xE2000000 DCR GPIO1_TSRL 0x0C000000 0x00200000 DCR GPIO1_ISR2L 0x00050000 0x00110000 Signed-off-by: Larry Johnson <lrj@acm.org>
* PPC4xx: Remove sdram.h from board/amcc/sequoiaLarry Johnson2008-01-04-505/+0
| | | | | | These definitions are now in "include/ppc440.h". Signed-off-by: Larry Johnson <lrj@acm.org>
* PPC4xx: Use common code for Sequoia board SDRAM supportLarry Johnson2008-01-04-338/+6
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* Add definitions for 440EPx/GRx SDRAM controller to ppc440.hLarry Johnson2007-12-27-2/+2
| | | | | | | | | This patch adds the Denali SDRAM controller definitions to "ppc440.h". It also fixes two typos in the definitions, so the board-specific "sdram.h" files containing these definitions are also fixed to avoid compiler warnings. Signed-off-by: Larry Johnson <lrj@acm.org>
* Use out_be32() and friends to access memory-mapped registers in sequoia.cLarry Johnson2007-12-27-29/+29
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* Use definitions from "asm-ppc/mmu.h" in init.S for SequoiaLarry Johnson2007-12-27-49/+1
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Bring 4xx fdt support up-to-dateStefan Roese2007-12-27-1/+24
| | | | | | | | This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAMStefan Roese2007-10-31-0/+4
| | | | | | | | | | | | | | This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add 667/133 (CPU/PLB) frequency setup to Sequoia bootstrap commandStefan Roese2007-10-18-1/+7
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix bug in I2C bootstrap values for Sequoia/RainierStefan Roese2007-10-15-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The I2C bootstrap values that can be setup via the "bootstrap" command, were setup incorrect regarding the generation of the internal sync PCI clock. The values for PLB clock == 133MHz were slighly incorrect and the values for PLB clock == 166MHz were totally incorrect. This could lead to a hangup upon booting while PCI configuration scan. This patch fixes this issue and configures valid PCI divisor values for the sync PCI clock, with respect to the provided external async PCI frequency. Here the values of the formula in the chapter 14.2 "PCI clocking" from the 440EPx users manual: AsyncPCICLK - 1MHz <= SyncPCIClk <= (2 * AsyncPCIClk) - 1MHz 33MHz async PCI frequency: PLB = 133: => 32 <= 44.3 <= 65 (div = 3) PLB = 166: => 32 <= 55.3 <= 65 (div = 3) 66MHz async PCI frequency: PLB = 133: => 65 <= 66.5 <= 132 (div = 2) PLB = 166: => 65 <= 83 <= 132 (div = 2) Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix incorrect 33/66MHz PCI clock log-message on Sequoia & YosemiteStefan Roese2007-10-15-3/+4
| | | | | | | | | | | The BCSR status bit for the 66MHz PCI operation was correctly addressed (MSB/LSB problem). Now the correct currently setup PCI frequency is displayed upon bootup. This patch also fixes this problem on Rainier & Yellowstone, since these boards use the same souce code as Sequoia & Yosemite do. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: (Re-)Enable CONFIG_PCI_PNP on AMCC 440EPx SequoiaGary Jennejohn2007-08-31-0/+3
| | | | | | | | | | | | | | | | | | | | | The 440EPx has a problem when the PCI_CACHE_LINE_SIZE register is set to non-zero, because it doesn't support MRM (memory-read- multiple) correctly. We now added the possibility to configure this register in the board config file, so that the default value of 8 can be overridden. Here the details of this patch: o drivers_pci_auto.c: introduce CFG_PCI_CACHE_LINE_SIZE to allow board-specific settings. As an example the sequoia board requires 0. Idea from Stefan Roese <sr@denx.de>. o board/amcc/sequoia/init.S: add a TLB mapping at 0xE8000000 for the PCI IO-space. Obtained from Stefan Roese <sr@denx.de>. o include/configs/sequoia.h: turn CONFIG_PCI_PNP back on and set CFG_PCI_CACHE_LINE_SIZE to 0. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update Sequoia/Rainier bootstrap commandStefan Roese2007-08-16-48/+157
| | | | | | | As suggested by David Mitchell, here an update for the Sequoia/Rainier bootstrap command. Signed-off-by: Stefan Roese <sr@denx.de>
* resubmit: ppc4xx: Remove sequoia/sequioa.h. Cleanup ppc440.h for PPC440EPXNiklaus Giger2007-07-04-72/+4
| | | | Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-06-25-0/+10
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| * Extend POST support for PPC440Igor Lisitsin2007-06-22-0/+10
| | | | | | | | | | | | | | Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
* | ppc4xx: Add pci_pre_init() for 405 boardsStefan Roese2007-06-25-15/+2
|/ | | | | | | | This patch removes the CFG_PCI_PRE_INIT option completely, since it's not needed anymore with the patch from Matthias Fuchs with the "weak" pci_pre_init() implementation. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add bootstrap command for AMCC Sequoia (440EPx) eval boardStefan Roese2007-06-19-1/+112
| | | | | | | | | | | This patch adds a board command to configure the I2C bootstrap EEPROM values. Right now 533 and 667MHz are supported for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 533 nor ;to configure the board for 533MHz NOR booting => bootstrap 667 nand ;to configure the board for 667MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-0/+4
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| * ppc4xx: Update Sequoia NAND booting support with ECCStefan Roese2007-06-01-0/+4
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Undo Sequoia patch for dynamic EBC speed support of 83MHzStefan Roese2007-06-01-6/+0
| | | | | | | | | | | | | | | | This patch undoes the patch by Jeff Mann with commit-id ada4697d. As suggested by AMCC it is not recommended to dynamically change the EBC speed after bootup. So we undo this change to be on the safe side. Signed-off-by: Stefan Roese <sr@denx.de>
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