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* ppc4xx: Add AMCC Arches board support (dual 460GT)Adam Graham2008-10-21-0/+140
| | | | | | | | | | | | | | The Arches Evaluation board is based on the AMCC 460GT SoC chip. This board is a dual processor board with each processor providing independent resources for Rapid IO, Gigabit Ethernet, and serial communications. Each 460GT has it's own 512MB DDR2 memory, 32MB NOR FLASH, UART, EEPROM and temperature sensor, along with a shared debug port. The two 460GT's will communicate with each other via shared memory, Gigabit Ethernet and x1 PCI-Express. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-24/+24
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ppc4xx: Canyonlands: Remove unnecessary FDT warning upon DTB fixupStefan Roese2008-09-22-12/+4
| | | | | | | | | Depending on the configuration jumper "SATA SELECT", U-Boot disabled either one PCIe node or the SATA node in the device tree blob. This patch removes the unnecessary and even confusing warning, when the node is not found at all. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Canyonlands: Disable the RTC M41T62 square wave outputStefan Roese2008-06-12-0/+11
| | | | | | | | | | | | | | | | | This patch disables the square wave output of the M41T62 RTC used on Canyonlands & Glacier. Here the explanation: The serial real-time clock part used in the design is an STMicro M41T62. This part has a full-time 32KHz square wave output that is connected to the TmrClk input to the processor. The default state for this square wave output is enabled so the output runs continuously when the board is powered normally and also from the battery. The TmrClk input to the processor goes to ground when the power is removed from the board/processor, and therefore the running square wave output is driving ground which drains the battery quickly. Signed-off-by: Stefan Roese <sr@denx.de>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-12-1/+1
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* ppc4xx: Remove implementations of testdram()Stefan Roese2008-06-03-38/+0
| | | | | | | This patch removes the used testdram() implementations of the board that are maintained by myself. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Canyonlands: Disable PCIe0/SATA in dev-tree depending on selectionStefan Roese2008-05-19-1/+30
| | | | | | | | | | | | | | | When SATA is selected (via jumper J6) we need to disable the first PCIe node in the device tree, so that Linux doesn't initialize it. Otherwise the Linux SATA driver will fail to detect the devices. The same goes the other way around too. So if PCIe is selected we need to disable the SATA node in the device tree. This is because PCIe port 0 and SATA on 460EX share the same pins (multiplexed) and we have to configure in U-Boot which peripheral is enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Canyonlands: Init SATA/PCIe port correctlyStefan Roese2008-04-02-12/+34
| | | | | | | | | Canyonlands (460EX) shares the first PCIe interface with the SoC SATA interface. This usage can be configured with the jumper J6. This patch correctly configures the SATA/PCIe PHY for SATA usage when this jumper is installed. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Canyonlands: Print SATA/PCIe configuration and board revisionStefan Roese2008-03-28-3/+39
| | | | | | | | | Canyonlands (460EX) shares the first PCIe interface with the SoC SATA interface. This usage can be configured with the jumper J6. This patch displays the current configuration upon bootup and changes the PCIe init loop, to only initialize the availabel PCIe slots. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Correctly pass phyiscal FLASH base address into dtbStefan Roese2008-03-27-1/+1
| | | | | | | | | The routine ft_board_setup() configures the EBC NOR mappings for the Linux physmap_of driver. Since on 460EX/GT we remap the FLASH from 0x4.fc00.0000 to 0x4.cc00.0000 because of the max. 16MByte boot-CS problem, we need to pass the corrected address here too. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add AMCC Glacier 406GT eval board supportStefan Roese2008-03-27-9/+16
| | | | | | | | | | | | | | This patch adds support for the AMCC Glacier 460GT eval board. The main difference to the Canyonlands board are listed here: - 4 ethernet ports instead of 2 - no SATA port - no USB port Currently EMAC2+3 are not working. This will be fixed in a later release. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add USB OHCI support to AMCC Canyonlands 460EX eval boardStefan Roese2008-03-15-0/+14
| | | | | | | This patch adds USB OHCI support to the Canyonlands board port. It also enables EXT2 support. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add Canyonlands NAND booting supportStefan Roese2008-03-15-4/+23
| | | | | | | | | | | | | | | 460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add AMCC Canyonlands support (460EX) (1/3)Stefan Roese2008-03-15-0/+385
This patch adds support for the AMCC Canyonlands 460EX evaluation board. Signed-off-by: Stefan Roese <sr@denx.de>