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* arm: socfpga: Update iomux and pll for c5 socdk RevEDinh Nguyen2016-05-10-36/+36
| | | | | | Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Fix i2c mux on cyclone5-socdk boardChin Liang See2015-12-23-2/+2
| | | | | | | | | | | | Updated pinmux group GENERALIO[15-16] for i2c. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: shengjiangwu <shengjiangwu@icloud.com>
* arm: socfpga: Fix USB doesn't work on socdk boardshengjiangwu2015-12-23-12/+12
| | | | | | | | | | | | Updated pinmux group EMACIO[1-8] and EMACIO[10-13] for USB. Signed-off-by: shengjiangwu <shengjiangwu@icloud.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de>
* arm: socfpga: Fix QSPI doesn't work on socdk boardshengjiangwu2015-12-22-7/+7
| | | | | | | | | | | | | Updated pinmux group MIXED1IO[15-20] for QSPI. Updated QSPI clock. Signed-off-by: shengjiangwu <shengjiangwu@icloud.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de>
* arm: socfpga: Fix emac1 doesn't work on socdk boardshengjiangwu2015-12-22-15/+15
| | | | | | | | | | | | | Updated pinmux group MIXED1IO[0-13] for RGMII1. Updated EMAC1 clock. Signed-off-by: shengjiangwu <shengjiangwu@icloud.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de>
* arm: socfpga: Drop the board boilerplateMarek Vasut2015-12-20-112/+0
| | | | | | | | Drop all the common board code, since it is not completely useless. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: cyclone5-socdk: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-2/+19
| | | | | | | | | | | | | | This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Lukasz Majewski <l.majewski@majess.pl> Cc: Lukasz Majewski <l.majewski@samsung.com>
* arm: socfpga: arria5-socdk: Probe DWC2 UDC from OF instead of hard-coded dataMarek Vasut2015-12-20-2/+19
| | | | | | | | | | | | | | This patch adds the necessary OF alias for the UDC node, which let's the code locate the DWC2 UDC base address in OF instead of hard-coding it into the U-Boot binary. The code is adjusted to use the address from OF instead of the hard-coded one. Finally, the hard-coded address is removed and USB DM support is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Lukasz Majewski <l.majewski@majess.pl> Cc: Lukasz Majewski <l.majewski@samsung.com>
* arm: socfpga: cyclone5-socdk: Remove Micrel PHY configurationMarek Vasut2015-12-20-40/+0
| | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: arria5-socdk: Remove Micrel PHY configurationMarek Vasut2015-12-20-40/+0
| | | | | | | | | | The Micrel PHY configuration is now done from OF, so hard-coding the configuration into the board file is no longer necessary. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* usb: s3c-otg: Rename usb/s3c_udc.h to usb/dwc2_udc.hMarek Vasut2015-12-17-2/+2
| | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch renames the global s3c_udc.h header to dwc2_udc.h. The rename is done automatically: $ sed -i "s/s3c_udc\.h/dwc2_udc.h/g" \ `git grep "s3c_udc\.h" | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename s3c_udc_probe() functionMarek Vasut2015-12-17-2/+2
| | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch is the second and final to rename global symbol, the s3c_udc_probe() function. The rename is done automatically: $ sed -i "s/s3c_udc_probe/dwc2_udc_probe/g" \ `git grep s3c_udc_probe | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
* usb: s3c-otg: Rename struct s3c_plat_otg_dataMarek Vasut2015-12-17-2/+2
| | | | | | | | | | | | The driver is actually for the Designware DWC2 controller. This patch is the first to rename global symbol, the struct s3c_plat_otg_data. The rename is done automatically: $ sed -i "s/s3c_plat_otg_data/dwc2_plat_otg_data/g" \ `git grep s3c_plat_otg_data | cut -d : -f 1` Signed-off-by: Marek Vasut <marex@denx.de>
* nios2: add 3c120 and 10m50 devboards MAINTAINERSThomas Chou2015-11-12-0/+13
| | | | | | | Add 3c120 and 10m50 devboards MAINTAINERS Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de>
* nios2: zap nios2-generic board dirThomas Chou2015-10-23-238/+0
| | | | | | | As we use device tree to control u-boot now, the generic board can be removed. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* nios2: zap initdramThomas Chou2015-10-23-5/+0
| | | | | | | Zap initdram(), as it is not used. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de>
* nios2: convert altera sysid to driver modelThomas Chou2015-10-23-1/+4
| | | | | | | | Convert altera sysid to driver model with misc uclass. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* nios2 : convert altera_pio to driver modelThomas Chou2015-10-23-12/+0
| | | | | | | | Convert altera_pio to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* nios2: move altera_pio_init to board_early_init_rThomas Chou2015-10-23-4/+9
| | | | | | | | As altera_pio_init() uses BSS, it should be moved to board_early_init_r(). Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de>
* arm: socfpga: update MAINTAINERS' file for cyclone5_socdk and arria5_socdkDinh Nguyen2015-09-23-4/+4
| | | | | | | | commit "arm: socfpga: rename socfpga_cyclone5 and socfpga_arria5 config files" renames the configs files, so we should update the MAINTAINERS' entry. At the same time, update the email for Dinh Nguyen. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Fix ArriaV SoCDK PLL configMarek Vasut2015-08-23-13/+13
| | | | | | | | Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot "rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into mainline to get a booting ArriaV SoCDK. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Fix MAINTAINERS entry for CV/AV SoCDKMarek Vasut2015-08-23-9/+4
| | | | | | Repair the maintainer entries so they match the current state of code. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Make the pinmux table const u8Marek Vasut2015-08-23-2/+2
| | | | | | | | | | | Now that we're actually converting the QTS-generated header files, we can even adjust their data types. A good candidate for this is the pinmux table, where each entry can have value in the range of 0..3, but each element is declared as unsigned long. By changing the type to u8, we can save over 600 Bytes from the SPL, so do it. This patch also constifies the array. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Switch to filtered QTS filesMarek Vasut2015-08-23-2952/+2538
| | | | Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Remove AV-specific parts from CV-SoCDKMarek Vasut2015-08-23-1153/+0
| | | | | | | Just remove the ArriaV specific parts from the CycloneV SoCDK board and they are no longer needed now. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Remove CV-specific parts from AV-SoCDKMarek Vasut2015-08-23-1117/+0
| | | | | | | Just remove the CycloneV specific parts from the ArriaV SoCDK board and they are no longer needed now. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Split Altera socfpga into AV and CV SoCDKMarek Vasut2015-08-23-0/+2771
| | | | | | | | | | | | | | | | | | The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Move wrappers into platform directoryMarek Vasut2015-08-23-539/+1
| | | | | | | | | Move the wrappers for QTS-generated files into platform directory out of the board directory. The trick here is to add -I to CFLAGS such that it points to the board directory in source tree and thus the qts/ directory there is still reachable. Signed-off-by: Marek Vasut <marex@denx.de>
* ddr: altera: sequencer: add RW_MGR_MEM_NUMBER_OF_RANKSDinh Nguyen2015-08-08-0/+1
| | | | | | | | | Fix build error for socfpga_cyclone5_defconfig: board/altera/socfpga/wrap_sdram_config.c:245:26: error: ‘RW_MGR_MEM_NUMBER_OF_RANKS’ undeclared here (not in a function) make[2]: *** [spl/board/altera/socfpga/wrap_sdram_config.o] Error 1 Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Wrap misc remaining macrosMarek Vasut2015-08-08-0/+21
| | | | | | | | | | | Introduce structure socfpga_sdram_misc_config to wrap the remaining misc configuration values in board file. Again, introduce a function, socfpga_get_sdram_misc_config(), which returns this the structure. This is almost the final step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Wrap IO_* macrosMarek Vasut2015-08-08-0/+23
| | | | | | | | | | | Introduce structure socfpga_sdram_io_config to wrap the IO configuration values in board file. Introduce socfpga_get_sdram_io_config() function, which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Wrap RW_MGR_* macrosMarek Vasut2015-08-08-0/+72
| | | | | | | | | | | Introduce structure socfpga_sdram_rw_mgr_config to wrap the RW manager configuration values in board file. Introduce a complementary function, socfpga_get_sdram_rwmgr_config(), which returns this the structure. This is another step toward wrapping the nasty QTS generated macros in board files and reducing the pollution of the namespace. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_initMarek Vasut2015-08-08-0/+15
| | | | | | | | | | Introduce two wrapper functions, socfpga_get_seq_ac_init() and socfpga_get_seq_inst_init() to avoid direct inclusion of the sequencer_auto_ac_init.h and sequencer_auto_inst_init.h QTS generated files. This reduces namespace pollution again. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sequencer: Move qts-generated files to board dirMarek Vasut2015-08-08-0/+601
| | | | | | | | Move the files generated by QTS into the board directory, they should not be part of the driver files at all. Signed-off-by: Marek Vasut <marex@denx.de> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* ddr: altera: sdram: Introduce socfpga_sdram_get_config()Marek Vasut2015-08-08-1/+187
| | | | | | | | | | Introduce socfpga_sdram_get_config() function implement in a board file, which returns the socfpga_sdram_config structure. This is the last step in cleaning up the socfpga_mmr_init_full(), but not the last step which allows removing the inclusion of sdram.h from drivers/ddr/altera/sdram.c thus far. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: system: Clean up pinmux_config.cMarek Vasut2015-08-08-8/+36
| | | | | | | | | | | | | | | Implement new accessor, sysmgr_get_pinmux_table(), used to obtain pinmux table and it's size from the QTS-generated pinmux_config.c. The target here is again to get rid of poluting global namespace by including the pinmux_config.h into it. Furthermore, the pinmux_config.h declares some CONFIG_HPS_* macros, which are explicitly useless to us in U-Boot. Instead, U-Boot does use DT to detect exactly these configuration options. This patch makes sure that while this QTS-generated file can stay in the tree, these obscure macros do not ooze into the namespace anymore. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: scan: Zap iocsr_scan_chain*_table()Marek Vasut2015-08-08-2/+43
| | | | | | | | | | | | | | | | | | | | | | Introduce accessor iocsr_get_config_table() for retrieving IOCSR config tables. This patch is again trimming down the namespace polution. The IOCSR config tables are used only by scan manager, they are generated by qts and are board specific. Before this patch, the approach to use these tables in scan manager was to define an extern variable to silence the compiler and compile board-specific iocsr_config.c into U-Boot which defined those extern variables. Furthermore, since these are tables and the scan manager needs to know the size of those tables, iocsr_config.h is included build-wide. This patch wraps all this into a single accessor which takes the scan chain ID and returns pointer to the table and it's size. All this is wrapped in wrap_iocsr_config.c board-specific file. The file includes the iocsr_config.c (!) to access the original tables and transitively iocsr_config.h . It is thus no longer necessary to include iocsr_config.h build-wide and the namespace polution is trimmed some more. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: clock: Clean up pll_config.hMarek Vasut2015-08-08-1/+145
| | | | | | | | | | | | | | | | | | | | | | | Extract the clock configuration horribleness caused by pll_config.h in the following manner. First of all, introduce a few new accessors which return values of various clocks used in clock_manager.c and use them in clock_manager.c . These accessors replace those few macros which came from pll_config.h originally. Also introduce an accessor which returns the struct cm_config default configuration for the clock manager used in SPL. The accessors are implemented in a board-specific wrap_pll_config.c file, whose sole purpose is to include the qts-generated pll_config.h and provide only the necessary values to the clock manager. The purpose of this design is to limit the scope of inclusion for the pll_config.h , which thus far was included build-wide and poluted the namespace. With this change, the inclusion is limited to just the new wrap_pll_config.c file, which in turn provides three simple functions for the clock_manager.c to use. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Move sdram_config.h to board dirMarek Vasut2015-08-08-0/+100
| | | | | | | This file is absolutelly positively board specific, so move it into the correct place. Signed-off-by: Marek Vasut <marex@denx.de>
* arm: socfpga: Move generated files into qts subdirMarek Vasut2015-08-08-1/+8
| | | | | | | | | Move all the files generated by Quartus into the qts/ subdir of the board/altera/socfpga dir to make them explicitly separate from the generic U-Boot code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
* ARM: socfpga: move board select into mach-socfpga/KconfigMasahiro Yamada2015-05-07-31/+0
| | | | | | | | | | Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: socfpga: do not add board directory to header search pathMasahiro Yamada2015-05-07-1/+1
| | | | | | | | | The compiler option "-Iboard/$(VENDOR)/$(BOARD)" just exists here for iocsr_config.c to be able to include iocsr_config.h. Use "..." instead of <...> to include a header in the same directory. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* arm: socfpga: spl: update peripheral pll for dev kitDinh Nguyen2015-04-21-1/+1
| | | | | | | | "commit 0d13a0051b2c arm: socfpga: Sync Cyclone V DK PLL configuration" mistakenly changed CONFIG_HPS_MAINPLLGRP_VCO_NUMER to 39, the correct value should be 79. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: spl: Add s_init stubDinh Nguyen2015-04-21-0/+2
| | | | | | | | | | Add a stub s_init function in the board file. The reason why the stub function is needed is that most of the work is now being done in board_init_f(), there is no need for the SPL to do anything s_init(). However, since lowlevel_init() is still branching to s_init(), we need stub function for now, until lowlevel_init() morphs into s_init(). Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: fix uart0 pin mux configurationDinh Nguyen2015-04-21-2/+2
| | | | | | | | | commit "07d30b6c3129 arm: socfpga: Sync Cyclone V DK pinmux configuration" incorrectly set the muxing for UART0 on the Cyclone V DK. This fixes it up so UART0 is working again. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
* arm: socfpga: Add Altera Arria V DK supportMarek Vasut2015-03-04-0/+928
| | | | | | | | | | | Add support for the Altera Arria V development kit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Zap board_early_init_f()Marek Vasut2015-03-04-8/+0
| | | | | | | | | | | Zap this unused empty function, no point in having it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Zap checkboard()Marek Vasut2015-03-04-9/+0
| | | | | | | | | | | | | Since all boards now have a DT, instead of hard-coding the board name into the U-Boot binary, read the board name from DT "model" property. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Drop cyclone5 suffix from board file nameMarek Vasut2015-03-04-1/+1
| | | | | | | | | | | | Drop the _cyclone5 suffix from socfpga_cyclone5.c since this file will contain Arria 5 support as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
* arm: socfpga: Sync Cyclone V DK PLL configurationMarek Vasut2015-03-04-23/+11
| | | | | | | | | | | | | | | Sync SoCFPGA Cyclone V development kit pinmux configuration with Rocketboard U-Boot v2013.01.01-114-g9381569 (ACDS14.1_REL_GSRD_PR). NOTE: This change is useless until we get proper SPL support, at which point this will likely need further rework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@opensource.altera.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pavel Machek <pavel@denx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Vince Bridgers <vbridger@opensource.altera.com>
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