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* ppc: amcc: Omit unneeded ns16550 CONFIG if using driver modelSimon Glass2015-02-12-0/+2
| | | | | | This comes from the device tree or a call to get_uart_clock(). Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: Allow the end of u-boot.bin to be foundSimon Glass2015-02-12-2/+6
| | | | | | | | Define an _end symbol indicating the end of u-boot.bin. Also add some dummy words into the link script to ensure that u-boot.bin will always extend that far. There may be a better way of doing this. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: Add a gpio.h header fileSimon Glass2015-02-12-0/+7
| | | | | | | This is required at present for device tree control. The ppc4xx does support GPIOs but does not seem to have a proper driver. So this file is empty. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: Call board_init_f_mem() for generic boardSimon Glass2015-02-12-1/+17
| | | | | | Call this function to set up our early memory. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: dts: Bring in canyonlands device tree filesSimon Glass2015-02-12-0/+1484
| | | | | | | The canyonlands.h config file works with canyonlands, glacier and arches boards. Bring in the device tree files for these from Linux 3.17. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: canyonlands: Move to generic boardSimon Glass2015-02-12-0/+2
| | | | | | Switch to generic board so that this board will not be broken/removed. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: Add ramboot config for glacierSimon Glass2015-02-12-0/+8
| | | | | | | Add a new ramboot config for glacier so that it is possible to test U-Boot loaded over Ethernet instead of using JTAG. Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: ppc4xx: canyonlands: config: Tidy up CONFIGs and config.mkSimon Glass2015-02-12-4/+1
| | | | | | | | Many CONFIG options have an unnecessary value of 1. CONFIG_440 is set in the various board config files. Also simplify the CONFIG_440 check in config.mk Signed-off-by: Simon Glass <sjg@chromium.org>
* powerpc: Permit device tree control of U-Boot (CONFIG_OF_CONTROL)Simon Glass2015-02-12-0/+1
| | | | | | | Enable this in the Kconfig so that PowerPC boards can use device tree to configure U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2015-02-10-149/+10646
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| * x86: Use tab instead of space to indent in PCIE_ECAM_BASEBin Meng2015-02-06-1/+1
| | | | | | | | | | | | | | | | Space is used before 'default' in PCIE_ECAM_BASE in arch/x86/Kconfig so it looks misaligned. Replace the space with tab to indent. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add SD/MMC support to quark/galileoBin Meng2015-02-06-0/+11
| | | | | | | | | | | | | | | | Intel Galileo board has a microSD slot which is routed from Quark SoC SDIO controller. Enable SD/MMC support so that we can use an SD card. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add SPI support to quark/galileoBin Meng2015-02-06-0/+30
| | | | | | | | | | | | | | | | | | | | The Quark SoC contains a legacy SPI controller in the legacy bridge which is ICH7 compatible. Like Tunnel Creek and BayTrail, the BIOS control register offset in the ICH SPI driver is wrong for the Quark SoC too, unprotect_spi_flash() is added to enable the flash write. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Add GPIO supportBin Meng2015-02-06-0/+14
| | | | | | | | | | | | | | | | | | | | Quark SoC has a legacy GPIO block in the legacy bridge (D0:F31), which is just the same one found in other x86 chipset. Since we programmed the GPIO register block base address, we should be able to enable the GPIO support on Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Initialize non-standard BARsBin Meng2015-02-06-0/+78
| | | | | | | | | | | | | | | | | | Quark SoC has some non-standard BARs (excluding PCI standard BARs) which need be initialized with suggested values. This includes GPIO, WDT, RCBA, PCIe ECAM and some ACPI register block base addresses. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Call MRC in dram_init()Bin Meng2015-02-06-2/+122
| | | | | | | | | | | | | | | | Now that we have added Quark MRC codes, call MRC in dram_init() so that DRAM can be initialized on a Quark based board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Enable the Memory Reference Code buildBin Meng2015-02-06-0/+1
| | | | | | | | | | | | | | Turn on the Memory Reference code build in the quark Makefile. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add System Memory Controller supportBin Meng2015-02-06-0/+3210
| | | | | | | | | | | | | | The codes are actually doing the memory initialization stuff. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add utility codes needed for MRCBin Meng2015-02-06-0/+2068
| | | | | | | | | | | | | | Add various utility codes needed for Quark MRC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add Memory Reference Code (MRC) main routinesBin Meng2015-02-06-0/+391
| | | | | | | | | | | | | | Add the main routines for Quark Memory Reference Code (MRC). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Bypass TSC calibrationBin Meng2015-02-06-0/+5
| | | | | | | | | | | | | | | | | | For some unknown reason, the TSC calibration via PIT does not work on Quark. Enable bypassing TSC calibration and override TSC_FREQ_IN_MHZ to 400 per Quark datasheet in the Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Allow overriding TSC_FREQ_IN_MHZBin Meng2015-02-06-20/+20
| | | | | | | | | | | | | | | | We should allow the value of TSC_FREQ_IN_MHZ to be overridden by the one in arch/cpu/<xxx>/Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Enable the Intel quark/galileo buildBin Meng2015-02-06-0/+18
| | | | | | | | | | | | | | | | | | Make the Intel quark/galileo support avaiable in Kconfig and Makefile. With this patch, we can generate u-boot.rom for Intel galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add basic Intel Galileo board supportBin Meng2015-02-06-0/+44
| | | | | | | | | | | | | | | | | | New board/intel/galileo board directory with minimum codes, plus board dts, defconfig and configuration files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add basic Intel Quark processor supportBin Meng2015-02-06-0/+295
| | | | | | | | | | | | | | | | Add minimum codes to support Intel Quark SoC. DRAM initialization is not ready yet so a hardcoded gd->ram_size is assigned. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add Cache-As-RAM initializationBin Meng2015-02-06-0/+105
| | | | | | | | | | | | | | | | | | Quark SoC contains an embedded 512KiB SRAM (eSRAM) that is initialized by hardware. eSRAM is the ideal place to be used for Cache-As-RAM (CAR) before system memory is available. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Define macros for pci configuration space accessBin Meng2015-02-06-7/+13
| | | | | | | | | | | | | | | | | | Move PCI_REG_ADDR and PCI_REG_DATA from arch/x86/lib/pci_type1.c to arch/x86/include/asm/pci.h, also define PCI_CFG_EN so that these macros can be used for pci configuration space access. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Add routines to access message bus registersBin Meng2015-02-06-0/+183
| | | | | | | | | | | | | | | | | | | | | | In the Quark SoC, some chipset commands are accomplished by utilizing the internal message network within the host bridge (D0:F0). Accesses to this network are accomplished by populating the message control register (MCR), Message Control Register eXtension (MCRX) and the message data register (MDR). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add header files for Intel Quark SoC definesBin Meng2015-02-06-0/+68
| | | | | | | | | | | | | | | | device.h for integrated pci devices' bdf on Quark SoC and quark.h for various memory-mapped and i/o-mapped base addresses within SoC. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add support for Intel Minnowboard MaxSimon Glass2015-02-06-2/+3831
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a relatively low-cost x86 board in a small form factor. The main peripherals are uSD, USB, HDMI, Ethernet and SATA. It uses an Atom 3800 series CPU. So far only the dual core 2GB variant is supported. This uses the existing FSP support. Binary blobs are required to make this board work. The microcode update is included as a patch (all 3000 lines of it). Change-Id: I0088c47fe87cf08ae635b343d32c332269062156 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow a UART to be set up before the FSP is readySimon Glass2015-02-06-0/+7
| | | | | | | | | | | | | | | | | | Since the FSP is a black box it helps to have some sort of debugging available to check its inputs. If the debug UART is in use, set it up after CAR is available. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow FSP Kconfig settings for all x86Simon Glass2015-02-06-38/+38
| | | | | | | | | | | | | | | | While queensbay is the first chip with these settings, others will want to use them too. Make them common. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Remove unnecessary casts and fix comment typosSimon Glass2015-02-06-5/+5
| | | | | | | | | | | | | | Tidy up the FSP support code a little. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: mmc: Move common FSP functions into a common fileSimon Glass2015-02-06-72/+59
| | | | | | | | | | | | | | | | | | | | | | | | Since these board functions seem to be the same for all boards which use FSP, move them into a common file. We can adjust this later if future FSPs need more flexibility. This creates a generic PCI MMC device. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Make CAR and DRAM FSP code commonSimon Glass2015-02-05-1/+3
| | | | | | | | | | | | | | | | | | For now this code seems to be the same for all FSP platforms. Make it common until we see what differences are required. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Adjust the FSP types slightlySimon Glass2015-02-05-7/+9
| | | | | | | | | | | | | | | | | | | | To avoid casts, find_fsp_header() should return a pointer. Add asmlinkage to two API functions which use that convention. UPD_TERMINATOR is common so move it into a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Move common FSP code into a common locationSimon Glass2015-02-05-8/+16
| | | | | | | | | | | | Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: video: Allow video ROM execution to fall back to the other methodSimon Glass2015-02-05-1/+2
| | | | | | | | | | | | | | | | If the BIOS emulator is not available, allow use of native execution if available, and vice versa. This can be controlled by the caller. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Rename MMCONF_BASE_ADDRESS and make it common across x86Simon Glass2015-02-05-2/+16
| | | | | | | | | | | | | | | | | | This setting will be used by more than just ivybridge so make it common. Also rename it to PCIE_ECAM_BASE which is a more descriptive name. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-02-10-408/+162
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| * | arm, at91: add reset controller status registerHeiko Schocher2015-02-07-0/+2
| | | | | | | | | | | | | | | | | | | | | add reset controller status register Signed-off-by: Heiko Schocher <hs@denx.de> Acked-by: Bo Shen <voice.shen@atmel.com>
| * | arm, at91, wdt: do not disable WDT in SPLHeiko Schocher2015-02-07-0/+4
| | | | | | | | | | | | | | | | | | | | | if CONFIG_AT91SAM9_WATCHDOG is set, do not disable WDT in SPL Signed-off-by: Heiko Schocher <hs@denx.de>
| * | ARM: atmel: cleanup: remove at91cap9 related codeBo Shen2015-02-07-407/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the at91cap9adk board is removed by commit: b5508344 (ARM: remove broken "at91cap9adk" board), so the at91cap9 code is not used anymore, and also the document for at91cap9 can not be found on www.atmel.com, so remove the at91cap9 related code. Signed-off-by: Bo Shen <voice.shen@atmel.com> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: atmel: sama5d4_xplained: enable spl supportBo Shen2015-02-07-0/+1
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4ek: enable SPL supportBo Shen2015-02-07-0/+1
| | | | | | | | | | | | | | | | | | | | | The sama5d4ek support boot up from NAND flash, SD/MMC card and also the SPI flash. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4: build related file when enable SPLBo Shen2015-02-07-0/+1
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4: can access DDR in interleave modeBo Shen2015-02-07-1/+1
| | | | | | | | | | | | | | | | | | The SAMAA5D4 SoC can access DDR in interleave mode. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4: add interrupt redirect functionBo Shen2015-02-07-0/+12
| | | | | | | | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com> [fix subject] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: atmel: sama5d4: add bus matrix init functionBo Shen2015-02-07-0/+35
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4: add matrix1 base addr definitionBo Shen2015-02-07-0/+2
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
generated by cgit v1.1 at 2024-11-09 20:38:59 +0000