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| * | ARM: atmel: spl: can not disable osc for sama5d4Bo Shen2015-02-07-0/+2
| | | | | | | | | | | | | | | | | | The SAMA5D4 SoC on chip rc oscillator can not be disabled. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: spl: add saic to aic redirect functionBo Shen2015-02-07-0/+8
| | | | | | | | | | | | | | | | | | | | | Some SoC need to redirect the saic to aic to make the interrupt to work, here add a weak function to be replaced by real function. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: spl: add weak bus matrix init functionBo Shen2015-02-07-0/+7
| | | | | | | | | | | | | | | | | | | | | Some SoC need to configure the bus matrix, add an weak function to be replace by real function. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5: add sfr register header fileBo Shen2015-02-07-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | The SFR (special function registers) can be shared bwteen sama5d3 and sama5d4 soc. Signed-off-by: Bo Shen <voice.shen@atmel.com> [whitespace adoptions for 80 char compliance] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: atmel: sama5: add bus matrix header fileBo Shen2015-02-07-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | This matrix header file can be shared between sama5d3 and sama5d4 soc. Signed-off-by: Bo Shen <voice.shen@atmel.com> [whitespace adaptions for 80 char compliance] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: atmel: clock: make it possible to configure HMX32Bo Shen2015-02-07-0/+8
| |/ | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-02-10-28/+309
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| * | arm: mxs: Add 'Wait for JTAG user' if booted in JTAG modeGraeme Russ2015-02-10-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When booting in JTAG mode, there is no way to use soft break-points, and no way of knowing when SPL has finished executing (so the user can issue a 'halt' command to load u-boot.bin for example) Add a debug output and simple loop to stop execution at the completion of the SPL initialisation as a pseudo break-point when booting in JTAG mode Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
| * | arm: mxs: Enable booting of mx28 without batteryGraeme Russ2015-02-10-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Section 4.1.2 of Freescale Application Note AN4199 describes the configuration required to operate the mx28 from a 5V source without a battery. This patch changes the behaviour of the dropout control of the DC-DC converter (refer to section 11.12.9 of the mx28 Application Processor Reference Manual - Document Number: MCIMX28RM, Rev 2, 08/2013) to the following: - Always use 4P2 Linear Regulator if CONFIG_SYS_MXS_VDD5V_ONLY is defined - Switch between 4P2 Linear Regulator and Battery, using whichever has the highest voltage if CONFIG_SYS_MXS_VDD5V_ONLY isnot set (this is the same as the pre-patch behaviour) Signed-off-by: Graeme Russ <gruss@tss-engineering.com> Signed-off-by: Damien Gotfroi <dgotfroi@greenwatch.be>
| * | arm: mxs: Add debug outputs and comments to mxs SPL source filesGraeme Russ2015-02-10-5/+127
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is difficult to track down fail to boot issues in the mxs SPL. Implement the following to make it easier: - Add debug outputs to allow tracing of SPL progress in order to track where failure to boot occurs. DEUBUG and CONFIG_SPL_SERIAL_SUPPORT must be defined to enable debug output in SPL - Add TODO comments where it is not clear if the code is doing what it is meant to be doing, even tough the board boots properly (these comments refer to existing code, not to any code added by this patch) Signed-off-by: Graeme Russ <gruss@tss-engineering.com>
| * | imx: mx6: Fixed AIPS3 base address issueYe.Li2015-02-10-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Should use AIPS3 configuration address 0x0227C000 to set AIPS3, not the AIPS3 base address. Additional, replace AIPS1_BASE_ADDR to AIPS3_ARB_BASE_ADDR to align with AIPS1 and AIPS2, and resolve the AIPS3_ARB_BASE_ADDR undefine problem. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | imx:mx6 update fuse_bank0_regsPeng Fan2015-02-10-4/+8
| | | | | | | | | | | | | | | | | | Update fuse_bank0_regs structure according reference mannual. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | ot1200: select SUPPORT_SPLChristian Gmeiner2015-01-22-0/+1
| | | | | | | | | | | | Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
| * | imx:mx6sx add dram io configure for mx6sxPeng Fan2015-01-22-14/+128
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define two structure mx6sx_iomux_ddr_regs and mx6sx_iomux_grp_regs. Add a new function mx6sx_dram_iocfg to configure dram io. Since mx6sx only have one channel mmdc0, define a new empty macro MMDC1 to replace mmdc1->entry=value for mx6sx. And to other mx6 soc, MMDC1 effects as "mmdc1->entry=value". Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | imx:mx6sxsabresd select SUPPORT_SPLPeng Fan2015-01-22-0/+1
| | | | | | | | | | | | | | | | | | select SUPPORT_SPL for mx6sxsabresd. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | arm: mx6: Add Barco platinum-picon and platinum-titaniumStefan Roese2015-01-19-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the new Barco platinum platform. It currently includes those two boards: platinum-titanium ----------------- This is the same board as the titanium that is already supported in mainline U-Boot. But its now moved to this new platform to support multiple "flavors" of imx6 boards in one directory. Its also moved to support SPL booting. And with this we use the run-time DDR configuration of this SPL support. The board is equipped with the Micron MT41J128M16JT-125 DDR chips. We now can remove the DDR related registers tuples from the imximage.cfg file. As all this is done in the SPL at run-time. platinum-picon -------------- This board is new and based on the MX6DL with 1GiB DDR using the Micron MT41K256M16HA DDR3 chips. Its also equipped with 2 NAND chips (each 512MiB). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Pieter Ronsijn <pieter.ronsijn@barco.com>
* | | Merge branch 'microblaze' of git://git.denx.de/u-boot-microblazeTom Rini2015-02-09-347/+271
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| * | | microblaze: spl: Add LISTS to linker scriptMichal Simek2015-02-09-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | This is required for driver model. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: spl: Do not call mem_malloc_init and use early allocMichal Simek2015-02-09-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch has some parts connected together: - Use _gd in bss section which is automatically cleared Location at SPL_MALLOC_END wasn't cleared at all - Use MALLOC_F_LEN(early alloc) instead of FULL MALLOC (mem_malloc_init is not called at all) - Simplify malloc and stack init. At the end of SPL addr is malloc area and below is stack Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Add support for CONFIG_SYS_MALLOC_F_LENMichal Simek2015-02-09-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Create space for dm_init where calloc is called and malloc_base has to be initialized. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Do not use CONFIG_SYS_GENERIC_GLOBAL_DATAMichal Simek2015-02-09-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because it is not compatible with DM where malloc_base has to be available early and init has to be done in ASM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Speedup code copyMichal Simek2015-02-09-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove one instruction in the loop which speedup code copying. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Move architecture to use generic board initMichal Simek2015-02-09-212/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Compile code with -fPIC to get GOT. Do not build SPL with fPIC because it increasing SPL size for nothing. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Fix gd_t address which is placed at the end of BRAMMichal Simek2015-02-09-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setup gd from ASM to be availalbe for board_init_r. Setting it up in spl_board_init is too late when MALLOC is used. Space for gd is located behind MALLOC area at the end of BRAM. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Remove unused asm labelMichal Simek2015-02-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | It is not used at all that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Use standard interrupt_init() functionMichal Simek2015-02-09-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | Do not use microblaze specific interrupt init function. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Remove unneeded data section adding from DTBMichal Simek2015-02-09-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DTB is added to rodata section: [ 2] .rodata PROGBITS 84c5b60c 05c60c 00c618 00 A 0 0 4 [ 3] .dtb.init.rodata PROGBITS 84c67c30 068c30 003c80 00 A 0 0 16 [ 4] .rela.dyn RELA 84c6b8b0 06c8b0 000534 0c A 0 0 4 [ 5] .data PROGBITS 84c6bde4 06cde4 001536 00 WA 0 0 16 Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Add debug message about enabling interruptsMichal Simek2015-02-09-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add one more debug message about enabling global interrupts. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Fix coding styleMichal Simek2015-02-09-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | No functional changes just to pass checkpatch.pl. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Remove DEBUG_INT macro and use debug() insteadMichal Simek2015-02-09-32/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not use specific macros for debugging. Also remove compilation warning: w+../arch/microblaze/cpu/interrupts.c: In function 'interrupt_handler': w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'void (*)(void *)' [-Wformat] w+../arch/microblaze/cpu/interrupts.c:153:2: warning: format '%x' expects argument of type 'unsigned int', but argument 4 has type 'void *' [-Wformat] Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Fix coding style in exception.cMichal Simek2015-02-09-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | Just coding style cleanup - no functional changes. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Show return address from exceptionMichal Simek2015-02-09-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Show also return address from exception which should suggest where the problem is. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | microblaze: Fix stack usage in interrupt handlerMichal Simek2015-02-09-61/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do not save registers below r1 stack pointer because it is not checked by stack undeflow is not able to detect it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | common: Move dram_init() declaration to common locationMichal Simek2015-02-09-9/+0
| | |/ | |/| | | | | | | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge git://git.denx.de/u-boot-arcTom Rini2015-02-09-24/+627
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| * | | arc: build libgcc in U-BootAlexey Brodkin2015-02-09-0/+528
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This way we may have very limited set of functions implemented so we save some space. Also it allows us to build U-Boot for any ARC core with the same one toolchain because we don't rely on pre-built libgcc. For example: * we may use little-endian toolchain but build U-Boot for ether endianess * we may use non-multilibbed uClibc toolchain but build U-Boot for whatever ARC CPU flavour that current GCC supports Private libgcc built from generic C implementation contributes only 144 bytes to .text section so we don't see significant degradation of size: --->8--- $ arc-linux-size u-boot.libgcc-prebuilt text data bss dec hex filename 222217 24912 214820 461949 70c7d u-boot.libgcc-prebuilt $ arc-linux-size u-boot.libgcc-private text data bss dec hex filename 222361 24912 214820 462093 70d0d u-boot.libgcc-private --->8--- Also I don't notice visible performance degradation compared to pre-built libgcc (where at least "*div*" functions are had-written in assembly) on typical operations of downloading 10Mb uImage over TFTP and bootm. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: move CPU flags selection to the main "config.mk"Alexey Brodkin2015-02-09-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As a preparation to ARCv2 port submission we're moving CPU slection flags to a common location. Also it will allow us to have more flexible CPU specification, not only ISA version but CPU family as well checking CONFIG_ARC_CPU_xxx. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: hard-code CONFIG_ARCH_EARLY_INIT_R in asm/config.hAlexey Brodkin2015-02-09-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Common arch_early_init_r() is used in "arc/lib/cpu.c" for all ARC boards so there's no sense in separate per-board definitions. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: hard-code CONFIG_SYS_GENERIC_BOARD into asm/config.hAlexey Brodkin2015-02-09-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There're no other options for ARC except "generic board" so ther's no point to define CONFIG_SYS_GENERIC_BOARD per board. We now have it set fo all ARC boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: add selection of endianess in KconfigAlexey Brodkin2015-02-09-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features. It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: select cache settings via menuconfigAlexey Brodkin2015-02-09-8/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change allows to keep board description clean and minimalistic. This is especially helpful if one board may house different CPUs with different features. It is applicable to both FPGA-based boards or those that have CPUs mounted on interchnagable daughter-boards. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: define and use PTAG AUX regs for MMUv3 onlyAlexey Brodkin2015-02-09-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | DC_PTAG and IC_PTAG registers only exist in MMUv3. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: add more flavours of ARC700 series CPUAlexey Brodkin2015-02-09-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now we may select a particular version of ARC700: * ARC750D or * ARC770D It allows more flexible (or more fine tuned) configuration of U-Boot. Before that change we relied on minimal configuration but now we may use specific features of each CPU. Moreover allows us to escape manual selection of options that exist in both CPUs but may have say different version like MMUv2 in ARC750D vs MMUv3 in ARC770D. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc: memcmp - fix zero-delay loop utilizationIgor Guryanov2015-02-09-0/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | It's prohibited to put branch instruction in the very end of zero-delay loop. On execution this causes "Illegal instruction" exception. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by: Igor Guryanov <guryanov@synopsys.com>
* | | Merge git://git.denx.de/u-boot-marvellTom Rini2015-02-06-0/+2295
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| * | | arm: mvebu: Add Serdes PHY config codeStefan Roese2015-02-06-0/+2114
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code is ported from the Marvell bin_hdr code into mainline SPL U-Boot. It needs to be executed very early so that the devices connected to the serdes PHY are configured correctly. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
| * | | arm: armada-xp: Add SPL support used to include the DDR training codeStefan Roese2015-02-06-0/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SPL support to the Marvell Armada-XP. With this addition the bin_hdr integration is not needed any more. The SPL will first initialize the serdes/PHY and the call the DDR setup and training code now integrated into mainline U-Boot. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
| * | | arm: db-mv784mp-gp: Enable SPL to include DDR training code into U-BootStefan Roese2015-02-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SPL support to the db-mv784mp-gp eval board. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
| * | | arm: maxbcm: Enable SPL to include DDR training code into U-BootStefan Roese2015-02-06-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds SPL support to the maxbcm MV78460 based board. Including the fixed DDR configuratrion needed for the DDR training code. And the the serdes PHY init code. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
| * | | arm: armada-xp: Change built target to include the SPL binary as bin_hdrStefan Roese2015-02-06-0/+4
| |/ / | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Luka Perkov <luka.perkov@sartura.hr>
generated by cgit v1.1 at 2024-11-12 23:23:06 +0000