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* EXYNOS5: Add structure for PMU registersRajeshwari Shinde2012-07-09-0/+622
| | | | | | | | This patch adds power mananagement registers structure for exynos5 SoC. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* EXYNOS5: Fix system register structureRajeshwari Shinde2012-07-09-0/+1
| | | | | | | | | This patch corrects the SYSREG structure. We have removed the sysreg.h added in the previous patchset version as the sysreg structure is already defined in system.h. Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Minkyu Kang <mk7.kang@samsung.com>
* USB: EXYNOS: Incorporate EHCI review commentsRajeshwari Shinde2012-07-09-5/+8
| | | | | | | This patch incorates the review comments given by Minkyu Kang for EHCI support on EXYNOS Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2012-07-08-459/+3059
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'master' of git://git.denx.de/u-boot-arm: (212 commits) ARM: cache: Move the cp15 CR register read before flushing the cache. ARM: introduce arch_early_init_r() PXA: Enable CONFIG_PREBOOT on zipitz2 ARM: mx28: Remove CONFIG_ARCH_CPU_INIT No need to define CONFIG_ARCH_CPU_INIT. add new board vl_ma2sc MTD: SPEAr SMI: Add write support for length < 4 bytes i2c: designware_i2c.c: Add support for the "i2c probe" command rtc/m41t62: Add support for M41T82 with HT (Halt Update) SPL: ARM: spear: Add SPL support for SPEAr600 platform Makefile: Add u-boot.spr build target (SPEAr) SPL: ARM: spear: Remove some objects from SPL build SPL: lib/Makefile: Add crc32.c to SPL build SPL: common/Makefile: Add image.c to SPL build arm: Don't use printf() in SPL builds GPIO: Add SPEAr GPIO driver net: Multiple updates/enhancements to designware.c cleanup/SPEAr: Define configuration flags more elegantly cleanup/SPEAr: Remove unnecessary parenthesis SPEAr: Correct SoC ID offset in misc configuration space SPEAr: explicitly select clk src for UART SPEAr: Remove CONFIG_MTD_NAND_VERIFY_WRITE to speed up NAND access SPEAr: Enable ONFI nand flash detection for spear3xx and 6xx and evb SPEAr: Enable CONFIG_SYS_FLASH_EMPTY_INFO macro SPEAr: Correct the definition of CONFIG_SYS_MONITOR_BASE SPEAr: Enable CONFIG_SYS_FLASH_PROTECTION SPEAr: Enable dcache for fast file transfer SPEAr: Enable autoneg for ethernet SPEAr: Enable udc and usb-console support only for usbtty configuration SPEAr: Enable usb device high speed support SPEAr: Initialize SNOR in early_board_init_f SPEAr: Change the default environment variables SPEAr: Remove unused flag (CONFIG_SYS_HZ_CLOCK) SPEAr: Add configuration options for spear3xx and spear6xx boards SPEAr: Add basic arch related support for SPEAr SoCs SPEAr: Add interface information in initialization SPEAr: Add macb driver support for spear310 and spear320 SPEAr: Configure network support for spear SoCs SPEAr: Place ethaddr write and read within CONFIG_CMD_NET SPEAr: Eliminate dependency on Xloader table SPEAr: Fix ARM relocation support st_smi: Fixed page size for Winbond W25Q128FV flash st_smi: Change timeout loop implementation st_smi: Fix bug in flash_print_info() st_smi: Change the flash probing method st_smi: Removed no needed dependency on ST_M25Pxx_ID st_smi: Fix smi read status st_smi: Move status register read before modifying ctrl register st_smi: Read status until timeout happens st_smi: Enhance the error handling st_smi: Change SMI timeout values st_smi: Return error in case TFF is not set st_smi: Add support for SPEAr SMI driver mtd/NAND: Remove obsolete SPEAr specific NAND drivers SPEAr: Configure FSMC driver for NAND interface mtd/NAND: Add FSMC driver support arm/km: remove calls to kw_gpio_* in board_early_init_f arm/km: add implementation for read_dip_switch arm/km: support the 2 PCIe fpga resets arm/km: skip FPGA config when already configured arm/km: redefine piggy 4 reg names to avoid conflicts arm/km: cleanup km_kirkwood boards arm/km: enable BOCO2 FPGA download support arm/km: remove portl2.h and use km_kirkwood instead arm/km: convert mgcoge3un target to km_kirkwood arm/km: add kmcoge5un board support arm/km: add kmnusa board support arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0 cm-t35: fix incorrect NAND_ECC layout selection ARM: OMAP4/5: Do not configure non essential pads, clocks, dplls. ARM: OMAP4/5: Move USB pads to essential list. ARM: OMAP4/5: Move USB clocks to essential group. ARM: OMAP4/5: Move gpmc clocks to essential group. ARM: OMAP4+: Move external phy initialisations to arch specific place. omap4: Use a smaller M,N couple for IVA DPLL da850/omap-l138: Enable auto negotiation in RMII mode omap: am33xx: accomodate input clocks other than 24 Mhz omap: emif: fix bug in manufacturer code test omap: emif: deal with rams that return duplicate mr data on all byte lanes OMAP4+: Force DDR in self-refresh after warm reset OMAP4+: Handle sdram init after warm reset ARM: OMAP3+: Detect reset type arm: bugfix: Move vector table before jumping relocated code Kirkwood: Add support for Ka-Ro TK71 arm/km: use spi claim bus to switch between SPI and NAND arm/kirkwood: protect the ENV_SPI #defines ARM: don't probe PHY address for LaCie boards lacie_kw: fix CONFIG_SYS_KWD_CONFIG for inetspace_v2 lacie_kw: fix SDRAM banks number for net2big_v2 Kirkwood: add lschlv2 and lsxhl board support net: add helper to generate random mac address net: use common rand()/srand() functions lib: add rand() function kwboot: boot kirkwood SoCs over a serial link kw_spi: add weak functions board_spi_claim/release_bus kw_spi: support spi_claim/release_bus functions kw_spi: backup and reset the MPP of the chosen CS pin kirkwood: fix calls to kirkwood_mpp_conf kirkwood: add save functionality kirkwood_mpp_conf function km_arm: use filesize for erase in update command arm/km: enable mii cmd arm/km: remove CONFIG_RESET_PHY_R arm/km: change maintainer for mgcoge3un arm/km: fix wrong comment in SDRAM config for mgcoge3un arm/km: use ARRAY_SIZE macro arm/km: rename CONFIG option CONFIG_KM_DEF_ENV_UPDATE arm/km: add piggy mac adress offset for mgcoge3un arm/km: add board type to boards.cfg AT91SAM9*: Change kernel address in dataflash to match u-boot's size ATMEL/PIO: Enable new feature of PIO on Atmel device ehci-atmel: fix compiler warning AT91: at91sam9m10g45ek : Enable EHCI instead OHCI Atmel : usb : add EHCI driver for Atmel SoC Fix: AT91SAM9263 nor flash usage Fix: broken boot message at serial line on AT91SAM9263-EK board i.MX6 USDHC: Use the ESDHC clock mx28evk: Fix boot by adjusting HW_DRAM_CTL29 register i.MX28: Add function to adjust memory parameters mx28evk: Fix PSWITCH key position mx53smd: Remove CONFIG_SYS_I2C_SLAVE definition mx53loco: Remove CONFIG_SYS_I2C_SLAVE definition mx53evk: Remove CONFIG_SYS_I2C_SLAVE definition mx53ard: Remove CONFIG_SYS_I2C_SLAVE definition mx35pdk: Remove CONFIG_SYS_I2C_SLAVE definition imx31_phycore: Remove CONFIG_SYS_I2C_SLAVE definition mx53ard: Remove unused CONFIG_MII_GASKET mx6: Avoid writing to read-only bits in imximage.cfg m28evk: use same notation to alloc the 128kB stack ... Signed-off-by: Wolfgang Denk <wd@denx.de>
| * ARM: cache: Move the cp15 CR register read before flushing the cache.SRICHARAN R2012-07-07-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following is the cleanup sequence in arch/arm/cpu/armv7/cpu.c int cleanup_before_linux(void) { ... ... dcache_disable(); v7_outer_cache_disable(); invalidate_dcache_all(); } 1) invalidate_dcache_all call expects that all the caches has been flushed, invalidated and there are no dirty entries prior to its execution. In the above sequence dcache_disable() flushes, invalidates the caches and turns off the mmu. But after it cleanups the cache and before the mmu is disabled there is a cp_delay() function which has STR instruction. On certain cores like the cortex-a15, cache hit and a write can happen to a cache line even when the dcache is disabled. So the above mentioned STR instruction creates a dirty entry after cleaning. The mmu gets disabled after this. 2) invalidate_dcache_all invalidates the cache lines. Again on cores like cortex-a15, invalidate instruction flushes the dirty line as well. So some times the dirty line from sequence 1 can corrupt the memory resulting in a crash. Fixing this by moving the get_cr() and cp_delay() calls before cleaning up the cache, thus avoiding the dirty entry. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * ARM: introduce arch_early_init_r()Fabio Estevam2012-07-07-0/+5
| | | | | | | | | | | | | | Introduce arch_early_init_r() function, which can be useful for doing early initialization after relocation has happened. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * ARM: mx28: Remove CONFIG_ARCH_CPU_INITFabio Estevam2012-07-07-2/+0
| | | | | | | | | | | | | | | | | | No need to define CONFIG_ARCH_CPU_INIT. All mx28 based boards should use arch_cpu_init(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * No need to define CONFIG_ARCH_CPU_INIT.Fabio Estevam2012-07-07-2/+0
| | | | | | | | | | | | | | All mx6 based boards should use arch_cpu_init(). Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * SPL: ARM: spear: Add SPL support for SPEAr600 platformStefan Roese2012-07-07-27/+1740
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds SPL support for SPEAr600. Currently only SNOR (Serial NOR) flash support is included. Other boot devices (NAND, MMC, USB ...) may be added with later patches. Tested on the STM SPEAr600 evaluation and x600 SPEAr600 boards. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Amit Virdi <amit.virdi@st.com> Cc: Vipin Kumar <vipin.kumar@st.com>
| * arm: Don't use printf() in SPL buildsSimon Glass2012-07-07-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | raise() likes to call printf() if it is available, but in SPL builds it either is not available, or adds a large chunk to the resulting image size. So don't call it even if it is available. This change reduces SPL size from 10KB to 6.3KB on hawkboard, for example, using generic relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Stefan Roese <sr@denx.de>
| * GPIO: Add SPEAr GPIO driverStefan Roese2012-07-07-0/+40
| | | | | | | | | | | | Tested on x600 (SPEAr600). Signed-off-by: Stefan Roese <sr@denx.de>
| * cleanup/SPEAr: Remove unnecessary parenthesisAmit Virdi2012-07-07-2/+2
| | | | | | | | | | | | | | | | | | In SPEAr configuration files, unnecessary paranthesis are used in some \#defines. Remove them as they serve no purpose Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * SPEAr: Correct SoC ID offset in misc configuration spaceShiraz Hashim2012-07-07-1/+1
| | | | | | | | | | | | | | | | | | | | SoC Core ID offset is 0x30 in miscellaneous configuration address space. It was wrongly mentioned as periph2 clk enable. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * SPEAr: explicitly select clk src for UARTShiraz Hashim2012-07-07-1/+8
| | | | | | | | | | | | | | | | | | | | UART in u-boot intends to run on 48MHz clock supplied by USB PLL. Explicitly select the intended clock source. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * SPEAr: Add basic arch related support for SPEAr SoCsVipin KUMAR2012-07-07-1/+91
| | | | | | | | | | | | | | | | | | | | | | Earlier, architecture specific init code was mixed with board initialization code in board/spear/... This patch updates architecture support for SPEAr in latest u-boot and prints the SoC information. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * SPEAr: Add macb driver support for spear310 and spear320Vipin KUMAR2012-07-07-0/+34
| | | | | | | | | | | | | | | | | | | | | | SPEAr310 and SPEAr320 SoCs have an extra ethernet controller. The driver for this device is already supported by u-boot, so configuring board configuration file and defining base addresses etc to make use of the common driver Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * SPEAr: Configure network support for spear SoCsVipin KUMAR2012-07-07-0/+1
| | | | | | | | | | | | Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * SPEAr: Eliminate dependency on Xloader tableAmit Virdi2012-07-07-74/+0
| | | | | | | | | | | | | | | | | | | | Xloader table was used primarily to inform u-boot about the DDR size. However, now the ddr size is calculated at runtime which eliminates any need for the Xloader table. So removing this unnecessary code. Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * st_smi: Add support for SPEAr SMI driverVipin KUMAR2012-07-07-115/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SMI is the serial memory interface controller provided by ST. Earlier, a driver exists in the u-boot source code for the SMI IP. However, it was specific to spear platforms. This commit converts the same driver to a more generic driver. As a result, the driver files are renamed to st_smi.c and st_smi.h and moved into drivers/mtd folder for reusability by other platforms using smi controller peripheral. Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * mtd/NAND: Remove obsolete SPEAr specific NAND driversVipin KUMAR2012-07-07-57/+0
| | | | | | | | | | | | | | | | | | | | | | Since, SPEAr platform uses generic FSMC driver now, so spear specific files drivers/mtd/nand/spr_nand.c, arch/arm/include/asm/arch-spear/spr_nand.h are removed Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
| * SPEAr: Configure FSMC driver for NAND interfaceVipin KUMAR2012-07-07-4/+4
| | | | | | | | | | | | | | | | | | | | | | Since FSMC is a standard IP and it supports different memory interfaces, it is supported independent of spear platform and spear is configured to use that driver for interfacing with the NAND device Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
| * arm: bugfix: save_boot_params_default accesses uninitalized stack when -O0Tetsuyuki Kobayashi2012-07-07-1/+7
| | | | | | | | | | | | | | | | save_boot_params_default() in cpu.c accesses uninitialized stack area when it compiled with -O0 (not optimized). Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Acked-by: Tom Rini <trini@ti.com>
| * ARM: OMAP4/5: Move USB clocks to essential group.SRICHARAN R2012-07-07-9/+7
| | | | | | | | | | | | | | | | | | USB clocks will be required for fastboot, tftp related functionalities. Move these clocks to essential group inorder to have the functionality working when non-essential clocks are not enabled. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * ARM: OMAP4/5: Move gpmc clocks to essential group.SRICHARAN R2012-07-07-2/+2
| | | | | | | | | | | | | | | | | | | | GPMC clocks are currently getting enabled as a part non-essential clocks. This will be required during NOR boot. Move this to essential group to keep the functionality, when non-essential clocks are not enabled. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * ARM: OMAP4+: Move external phy initialisations to arch specific place.SRICHARAN R2012-07-07-27/+39
| | | | | | | | | | | | | | | | | | | | The external phy is present in the case OMAP5 soc is currently configured in emif-common.c. This results in having dummy structures for those Socs which do not have a external phy. So by having a weak function in emif-common and overriding it in OMAP5, avoids the use of dummy structures. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * omap4: Use a smaller M,N couple for IVA DPLLSebastien Jan2012-07-07-1/+1
| | | | | | | | | | | | | | | | | | | | This reduced M,N couple corresponds to the advised value from TI HW team. Tested on 4460 Pandaboard, it also provides peripheral clocks closer to the advised values. Signed-off-by: Sebastien Jan <s-jan@ti.com>
| * omap: am33xx: accomodate input clocks other than 24 MhzSteve Sakoman2012-07-07-5/+5
| | | | | | | | | | | | | | | | | | The PLL setup values currently assume a 24 Mhz input clock. This patch uses V_OSCK from the board config file to support boards with different input clock rates. Signed-off-by: Steve Sakoman <steve@sakoman.com>
| * omap: emif: fix bug in manufacturer code testSteve Sakoman2012-07-07-1/+1
| | | | | | | | | | | | | | Code currently tests for <= 0xff. Micron manufacturer code is 0xff, so Micron memory will not be detected! Signed-off-by: Steve Sakoman <steve@sakoman.com>
| * omap: emif: deal with rams that return duplicate mr data on all byte lanesSteve Sakoman2012-07-07-1/+6
| | | | | | | | | | | | | | | | | | | | Some rams (Micron for example) return duplicate mr data on all byte lanes. Users of the get_mr function currently don't deal with this duplicated data gracefully. This patch detects the duplicated data and returns only the expected 8 bit mr data. Signed-off-by: Steve Sakoman <steve@sakoman.com>
| * OMAP4+: Force DDR in self-refresh after warm resetLokesh Vutla2012-07-07-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Errata ID:i727 Description: The refresh rate is programmed in the EMIF_SDRAM_REF_CTRL[15:0] REG_REFRESH_RATE parameter taking into account frequency of the device. When a warm reset is applied on the system, the OMAP processor restarts with another OPP and so frequency is not the same. Due to this frequency change, the refresh rate will be too low and could result in an unexpected behavior on the memory side. Workaround: The workaround is to force self-refresh when coming back from the warm reset with the following sequence: • Set EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2 • Set EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM to 0x0 • Do a dummy read (loads automatically new value of sr_tim) This will reduce the risk of memory content corruption, but memory content can't be guaranteed after a warm reset. This errata is impacted on OMAP4430: 1.0, 2.0, 2.1, 2.2, 2.3 OMAP4460: 1.0, 1.1 OMAP4470: 1.0 OMAP5430: 1.0 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
| * OMAP4+: Handle sdram init after warm resetLokesh Vutla2012-07-07-4/+6
| | | | | | | | | | | | | | | | | | | | EMIF and DDR device state are preserved in warmreset. Redoing the full initialisation would cause unexpected behaviour. Do only partial initialisation to account for frequency change. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
| * ARM: OMAP3+: Detect reset typeLokesh Vutla2012-07-07-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | Certain modules are not affected by means of a warm reset and need not be configured again. Adding an API to detect the reset reason warm/cold. This will be used to skip the module configurations that are retained across a warm reset. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * arm: bugfix: Move vector table before jumping relocated codeTetsuyuki Kobayashi2012-07-07-0/+12
| | | | | | | | | | | | | | | | | | | | Interrupts and exceptions doesn't work in relocated code. It badly use IRQ_STACK_START_IN in rom area as interrupt stack. It is because the vecotr table is not moved to ram area. This patch moves vector table before jumping relocated code. Signed-off-by: Tetsuyuki Kobayashi <koba@kmckk.co.jp> Tested-by: Tom Rini <trini@ti.com>
| * arm/kirkwood: protect the ENV_SPI #definesValentin Longchamp2012-07-07-3/+9
| | | | | | | | | | | | | | | | So that they can be redefined by some boards specific values. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
| * kw_spi: support spi_claim/release_bus functionsValentin Longchamp2012-07-07-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | These two function nows ensure that the MPP is configured correctly for the SPI controller before any SPI access, and restore the initial configuration when the access is over. Since the used pins for the SPI controller can differ (2 possibilities for each signal), the used pins are configured with CONFIG_SYS_KW_SPI_MPP. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
| * kirkwood: add save functionality kirkwood_mpp_conf functionValentin Longchamp2012-07-07-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If a second non NULL argument is given to the kirkwood_mpp_conf function, it will be used to store the current configuration of the MPP registers. mpp_save must be a preallocated table of the same size as mpp_list and it must be zero terminated as well. A later call to kirkwood_mpp_conf function with this saved list as first (mpp_conf) argment will set the configuration back. Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Holger Brunck <holger.brunck@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
| * ATMEL/PIO: Enable new feature of PIO on Atmel deviceBo Shen2012-07-07-1/+44
| | | | | | | | | | | | | | | | Enable new PIO feature supported by Atmel SoC. Using CPU_HAS_PIO3 micro to enable PIO new feature. Signed-off-by: Bo Shen <voice.shen@atmel.com> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * i.MX6 USDHC: Use the ESDHC clockMichael Langer2012-07-07-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit "i.mx: fsl_esdhc: add the i.mx6q support" (4692708d) introduces support for the i.MX6Q MMC host controller USDHC. MXC_IPG_PERCLK sets the clock to 66MHz. This seems to be the default clock of the ESDHC IP found in < i.MX6 silicon. However, the default clock for the USDHC IP found in i.MX6 is 200MHz (MXC_ESDHC_CLK). This difference will cause a 3 times higher clock on SD_CLK than expected (see fsl_esdh.c -> set_sysctl()). Signed-off-by: Michael Langer <michael.langer@de.bosch.com> CC: Stefano Babic <sbabic@denx.de> CC: Jason Liu <r64343@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * i.MX28: Add function to adjust memory parametersMarek Vasut2012-07-07-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This function can be overridden at run-time and allows implementors of new boards based on the i.MX28 chip to fine-tune the memory params. It is possible to write into the dram_vals array because when the SPL runs, it is located SRAM. Therefore the location is writable. There is no possibility of these data to be read-only. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Detlev Zundel <dzu@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <festevam@gmail.com>
| * MX28: Fix a typo in mx28_reg_8 macroOtavio Salvador2012-07-07-1/+1
| | | | | | | | | | | | | | | | | | The macro mistakenly referred to 32bit struct instead of 8bit one. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Marek Vasut <marex@denx.de> Acked-by: Marek Vasut <marex@denx.de>
| * mx53: Fix mask for SATA reference clockFabio Estevam2012-07-07-1/+1
| | | | | | | | | | | | | | | | SATA_ALT_REF_CLK field corresponds to bits 1 and 2 of offset 0x180c. Fix the mask for these bits. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
| * i.mx: i.mx6x: NO_MUX_I/NO_PAD_I not set correctlyJason Liu2012-07-07-2/+2
| | | | | | | | | | | | | | | | | | If one PAD does not have mux or pad config register, we need set the NO_MUX_I/NO_PAD_I to 0, the old value is not correct Signed-off-by: Jason Liu <jason.hui@linaro.org> CC: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * EXYNOS5: PINMUX: Added default pinumx settingsRajeshwari Shinde2012-07-07-1/+326
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch performs the pinmux configuration in a common file. As of now only EXYNOS5 pinmux for SDMMC, UART and Ethernet is supported. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Che-Liang Chiou <clchiou@chromium.org> Signed-off-by: Rajeshwari Shinde <rajeshwari.s@samsung.com> Acked-by: Chander Kashyap <chander.kashyap@linaro.org> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Exynos: fix cpuinfo and cpu detectingMinkyu Kang2012-07-07-16/+37
| | | | | | | | | | | | | | | | | | | | Since Exynos architecture have new SoCs, need to fix cpuinfo correctly. Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Cc: Chander Kashyap <chander.kashyap@linaro.org>
| * ARM: OMAP4: Correct the lpddr2 io settings register value.SRICHARAN R2012-07-07-1/+1
| | | | | | | | | | | | | | | | | | | | To meet certain timing requirements on the lpddr2 cmd and data phy interfaces ,lpddr iopads have to be configured as differential buffers and a Vref has to be internally generated and provided to these buffers. Correcting the above settings here. Signed-off-by: R Sricharan <r.sricharan@ti.com>
| * OMAP5: Change voltages for omap5432Lokesh Vutla2012-07-07-10/+31
| | | | | | | | | | | | Change voltages for OMAP5432 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * OMAP5: DPLL core lock for OMAP5432Lokesh Vutla2012-07-07-6/+25
| | | | | | | | | | | | | | No need to Unlock DPLL initially. DDR3 can work at normal OPP from initialozation Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * OMAP5: EMIF: Add support for DDR3 deviceLokesh Vutla2012-07-07-4/+166
| | | | | | | | | | | | | | | | | | In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * OMAP5: ADD precalculated timings for ddr3Lokesh Vutla2012-07-07-1/+55
| | | | | | | | | | | | | | Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3 Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * OMAP5: Configure the io settings for omap5432 uevm boardLokesh Vutla2012-07-07-20/+93
| | | | | | | | | | | | This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
generated by cgit v1.1 at 2024-11-12 00:47:42 +0000