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* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-02-24-9/+18
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| * arm: socfpga: Fix ethernet reset handlingMarek Vasut2016-02-24-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following patch caused cpu_eth_init() to not be called anymore for DM-capable boards: commit c32a6fd07b1839e4a45729587ebc8e1c55601a4d Date: Sun Jan 17 14:51:56 2016 -0700 net: Don't call board/cpu_eth_init() with driver model This breaks ethernet on SoCFPGA, since we use that function to un-reset the ethernet blocks. Invoke the ethernet reset function from arch_misc_init() instead to fix the breakage. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
| * arm: socfpga: Remove bashisms from qts filterMarek Vasut2016-02-24-7/+7
| | | | | | | | | | | | | | | | | | | | Weed out bashisms from the script. The echo -e does not work in dash, which is the default /bin/sh in debian . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Dalon Westergreen <dwesterg@gmail.com>
| * arm: socfpga: cv_socdk: Add support for QSPI bootMarek Vasut2016-02-24-0/+2
| | | | | | | | | | | | | | | | | | Add missing DT nodes to allow booting from QSPI NOR. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
| * arm: socfpga: av_socdk: Add support for QSPI bootMarek Vasut2016-02-24-0/+2
| | | | | | | | | | | | | | | | | | Add missing DT nodes to allow booting from QSPI NOR. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Chin Liang See <clsee@altera.com> Cc: Denis Bakhvalov <denis.bakhvalov@nokia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-02-24-133/+805
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| * | armv7: ls102xa: Move smmu and stream id initialization into the common soc codeAlison Wang2016-02-24-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | The initialization for smmu and stream id is moved into the common soc code. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/fsl-layerscape: fdt: add fixup for Fman ucodeQianyu Gong2016-02-24-0/+7
| | | | | | | | | | | | | | | | | | | | | Add fdt fixup to insert Fman firmware into the device tree. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | fm: fdt: Move fman ucode fixup to driver codeQianyu Gong2016-02-24-120/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | Not only powerpc/mpc85xx but also Freescale Layerscape platforms will use fdt_fixup_fman_firmware() to insert Fman ucode blob into the device tree. So move the function to Fman driver code. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | qe: move drivers/qe/qe.h to include/fsl_qe.hQianyu Gong2016-02-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | As the QE firmware struct is shared with Fman, move the header file out of drivers/qe/. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043a: Implement workaround for erratum A009660Mingkai Hu2016-02-24-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | Memory controller performance is not optimal with default internal target queue register value, write required value for optimal DDR performance. Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043a: enable workaround for errarum A009942Shengzhou Liu2016-02-24-0/+1
| | | | | | | | | | | | | | | | | | | | | DDR erratum A-009942 applies to LS1043A. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc/SECURE_BOOT: Add PAMU driverAneesh Bansal2016-02-24-9/+686
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PAMU driver basic support for usage in Secure Boot. In secure boot PAMU is not in bypass mode. Hence to use any peripheral (SEC Job ring in our case), PAMU has to be configured. The patch reverts commit 7cad2e38d61e27ea59fb7944f7e647e97ef292d3. The Header file pamu.h and few functions in driver have been derived from Freescale Libos. Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arm: ls1021aqds: Enable driver model lpuart serial driverYork Sun2016-02-24-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Convert ls1021aqds_nor_lpuart and ls1021aqds_ddr4_nor_lpuart to driver model suport. Enable lpuart port driver. Signed-off-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alison Wang <alison.wang@nxp.com>
| * | arm: ls1021aqds: Convert to driver model and enable serial supportYork Sun2016-02-23-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Split duart configuration as device tree file. Move /chosen node out of board commone device tree. Convert ls1021aqds nor and SD configurations to driver model support (qspi already uses DM). Enable ns16550 DM serial driver for nor configurations. Signed-off-by: York Sun <york.sun@nxp.com> CC: Alison Wang <alison.wang@nxp.com> CC: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alison Wang <alison.wang@nxp.com>
* | | microblaze: Add missing chosen nodeMichal Simek2016-02-24-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fdtgrep requires /chosen node to be specified or at least more nodes which stays in DTS to generate output. Error message: ./tools/fdtgrep -b u-boot,dm-pre-reloc -RT dts/dt.dtb -n /chosen -O dtb | ./tools/fdtgrep -r -O dtb - -o spl/u-boot-spl.dtb -P pinctrl-0 -P pinctrl-names -P clocks -P clock-names -P interrupt-parent Error: FDT_ERR_BADMAGIC This patch add empty chosen node to keep fdtgrep happy and pass compilation for in tree DTS file. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | rpi: set board serial number in environmentLubomir Rintel2016-02-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Gets propagated into the device tree and then into /proc/cpuinfo where users often expect it. Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Tested-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Stephen Warren <swarren@wwwdotorg.org>
* | | stm32: add support for stm32f7 & stm32f746 discovery boardVikas Manocha2016-02-24-0/+535
| | | | | | | | | | | | | | | | | | This patch adds support for stm32f7 family & stm32f746 board. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | | gpio: stm32_gpio: move base addresses to the soc fileVikas Manocha2016-02-24-0/+18
| | | | | | | | | | | | | | | | | | | | | Base addresses for GPIOs could be different for different socs, this patch moves the base addresses from driver to the soc specific location. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | | gpio: stm32_gpio: move clock config from driver to boardVikas Manocha2016-02-24-0/+59
| |/ |/| | | | | | | | | | | This patch removes the gpio clock enable from gpio driver & move it in the board code, making it possible to use the gpio driver with other socs. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-02-23-7/+58
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| * | sunxi: H3: Add support for the host usb-physJelle van der Waa2016-02-23-7/+58
| |/ | | | | | | | | | | | | | | Add support for phy 1-3. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> [hdegoede@redhat.com: use setclrbits_le32 instead of read-modify-write] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: zynq: Add reset-gpio property for USB on ZyboMichal Simek2016-02-22-1/+2
| | | | | | | | | | | | | | | | DTS syncup with Linux kernel. Add missing reset-gpio property. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Enable u-boot,dm-pre-reloc for qspiNathan Rossi2016-02-22-0/+3
| | | | | | | | | | | | | | | | | | | | Enable u-boot,dm-pre-reloc for qspi for zc706, zed and microzed. Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: Remove unused SPI base addressesMichal Simek2016-02-22-5/+0
|/ | | | | | | | Remove unused macros. Adresses are taken from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jagan Teki <jteki@openedev.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-02-21-3/+938
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| * imx: mx7d: isolate resources to domain 0 for A7 corePeng Fan2016-02-21-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current design, if any peripheral was assigned to both A7 and M4, it will receive ipg_stop or ipg_wait when any of the 2 platforms enter low power mode. We will have a risk that, if A7 enter wait, M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait asserted same time. Also if M4 enters stop mode, A7 will have no chance to access the peripheral. There are 26 peripherals affected by this IC issue: SIM2(sim2/emvsim2) SIM1(sim1/emvsim1) UART1/UART2/UART3/UART4/UART5/UART6/UART7 SAI1/SAI2/SAI3 WDOG1/WDOG2/WDOG3/WDOG4 GPT1/GPT2/GPT3/GPT4 PWM1/PWM2/PWM3/PWM4 ENET1/ENET2 Software Workaround: The solution is to set the peripherals to Domain0 by A core, since A core in Domain0. The peripherals which will be used by M4, will be set to Domain1 by M4. For example, A core set WDOG4 to domain0, but when M4 boots up, M4 will set WDOG4 to domain1, because M4 will use WDOG4. So the peripherals are not shared by them. This way requires the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only. M4 image will set the M4 to domain 1 and set peripheral which it will use to domain 1. This patch enables the CONFIG_IMX_RDC and CONFIG_IMX_BOOTAUX for i.MX7D SABRESD board, and setup the 26 IP resources to domain 0. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7: implement functions to boot auxiliary corePeng Fan2016-02-21-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6: implement functions to boot auxiliary corePeng Fan2016-02-21-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | Implement arch_auxiliary_core_up and arch_auxiliary_core_check_up. arch_auxiliary_core_check_up is used to check whether M4 is running or not. arch_auxiliary_core_up is to boot M4 core, the m4 core will use the pc and stack which is set in arch_auxiliary_core_up to set R15 and R13 register and boot. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: imx-common: introduce boot auxiliary corePeng Fan2016-02-21-0/+79
| | | | | | | | | | | | | | | | | | | | | | To boot a auxiliary core in asymmetric multicore system, introduce the new command "bootaux" to do it. Example of boot auxliary core from 0x70000000 where stores the boot head information that should be parsed by auxiliary core, "bootaux 0x70000000". Introduce Kconfig option IMX_BOOTAUX. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7d: clock support for RDCPeng Fan2016-02-21-0/+6
| | | | | | | | | | | | If CONFIG_IMX_RDC is enabled, enable clock for RDC and SEMAPHORE. Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx7d: Add RDC supportPeng Fan2016-02-21-0/+182
| | | | | | | | | | | | | | | | Add the peripherals/masters definitions and registers base addresses for mx7d RDC. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6sx Add RDC mappings of masters and peripheralsPeng Fan2016-02-21-0/+159
| | | | | | | | | | | | | | Add the definitions for the RDC mappings for i.MX6 SoloX. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: imx-common: introduce Resource Domain Controller supportPeng Fan2016-02-21-0/+304
| | | | | | | | | | | | | | | | | | Introduce Resource Domain Controller support for i.MX. Now i.MX6SX and i.MX7D supports this feature to assign masters and peripherals to different domains. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6: introduce rdc regsPeng Fan2016-02-21-0/+24
| | | | | | | | | | | | | | | | Introudce rdc regs structure and rdc sema reg structure for i.MX6. For now, to i.MX6, only i.MX6SX supports this. Signed-off-by: Ye.Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
| * imx: mx6: Implement mmc_get_env_partSoeren Moch2016-02-21-3/+33
| | | | | | | | | | | | | | | | | | | | commit 216d286c7e3d3d83d4d8ccaf0415192e1b1040c0 [imx: mx6: implement mmc_get_env_dev] introduced selection of the environment device according to the boot device when booting from SD/MMC. Extend this functionality for also selecting the device partition. Signed-off-by: Soeren Moch <smoch@web.de>
| * imx: Refactoring CAAM Job Ring structure and Secure Memory for imx7Ulises Cardenas2016-02-21-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Refactored data structure for CAAM's job ring and Secure Memory to support i.MX7. The new memory map use macros to resolve SM's offset by version. This will solve the versioning issue caused by the new version of secure memory of i.MX7 Signed-off-by: Ulises Cardenas <raul.casas@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* | x86: Add Intel Cougar Canyon 2 boardBin Meng2016-02-21-0/+109
| | | | | | | | | | | | | | | | | | This adds basic support to Intel Cougar Canyon 2 board, a board based on Chief River platform with an Ivy Bridge processor and a Panther Point chipset. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: ivybridge: bd82x6x: Support FSP enabled configurationBin Meng2016-02-21-1/+5
| | | | | | | | | | | | | | | | Wrap initialization codes with #ifndef CONFIG_HAVE_FSP #endif, and enable the build for both FSP and non-FSP configurations. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | x86: fsp: Make sure HOB list is not overwritten by U-BootBin Meng2016-02-21-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel IvyBridge FSP seems to be buggy that it does not report memory used by FSP itself as reserved in the resource descriptor HOB. The FSP specification does not describe how resource descriptor HOBs are generated by the FSP to describe what memory regions. It looks newer FSPs like Queensbay and BayTrail do not have such issue. This causes U-Boot relocation overwrites the important boot service data which is used by FSP, and the subsequent call to fsp_notify() will fail. To resolve this, we find out the lowest memory base address allocated by FSP for the boot service data when walking through the HOB list in fsp_get_usable_lowmem_top(). Check whether the memory top address is below the FSP HOB list, and if not, use the lowest memory base address allocated by FSP as the memory top address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
* | x86: ivybridge: Add FSP supportBin Meng2016-02-21-0/+131
| | | | | | | | | | | | | | | | | | | | IvyBridge FSP package is built with a base address at 0xfff80000, and does not use UPD data region. This adds basic FSP support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested on link (ivybridge non-FSP) Tested-by: Simon Glass <sjg@chromium.org>
* | x86: fix memalign() parameter orderStephen Warren2016-02-21-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Purely by code inspection, it looks like the parameter order to memalign() is swapped; its parameters are (align, size). 4096 is a likely desired alignment, and a variable named size sounds like a size:-) Fixes: 45b5a37836d5 ("x86: Add multi-processor init") Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-02-20-254/+307
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| * | ARM: Add Support for the VInCo platformGregory CLEMENT2016-02-19-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Versatile Industrial Communication platform is a community oriented board from Landis + Gyr. It comes with: - an RS-485 port - 2 Ethernet ports - a wireless M-BUS - a 4G modem - a 4MB SPI flash - a 4GB eMMC Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> [rebase on current TOT] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: sama5d2: configure the L2 cache memorySamuel Mescoff2016-02-18-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SAMA5D2 has a second internal SRAM that can be reassigned as a L2 cache memory. Make sure it is configured as a L2 cache memory when booting from a SPL image. Based on the commit b5ea95ef2b5b from the at91bootstrap repository. Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr> Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | arm: at91: Add support for DENX MA5D4 SoM and EVKMarek Vasut2016-02-18-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for DENX MA5D4 SoM and MA5D4EVK board, based on the Atmel SAMA5D4 SoC. The SoM contains the SoC, eMMC, SPI NOR, SPI CAN controllers and DRAM, the baseboard contains UART connectors, ethernet port, microSD slot, LCD header, 2x CAN connector and a lot of expansion headers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: clean up the PMC_PLLICPR init codeWenyou Yang2016-02-18-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to introducing the PMC_PLLICPR init function, use this function to clean up the code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: clock: add PMC_PLLICPR init functionWenyou Yang2016-02-18-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | To avoid the duplicated code, add the PMC_PLLICPR init function. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: clock: add PLLB enable/disable functionsWenyou Yang2016-02-18-0/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To avoid the duplicated code, add the PLLB handle functions. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com> Tested-by: Heiko Schocher <hs@denx.de> [add enable/disable functions to arm920t] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | ARM: at91: armv7: clean up UTMI PLL handle codeWenyou Yang2016-02-18-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to introducing the UTMI PLL enable function, use this function to reduce the duplicated code. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
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