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* Merge git://git.denx.de/u-boot-dmTom Rini2016-07-15-52/+378
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| * rockchip: sdram: Update the driver to support of-platdataSimon Glass2016-07-14-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | Add support for of-platdata with rk3288 SDRAM initr. This requires decoding the of-platdata struct and setting up the device from that. Also the driver needs to be renamed to match the string that of-platdata will search for. The platform data is copied from the of-platdata structure to the one used by the driver. This allows the same code to be used with device tree and of-platdata. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: sdram: Move all DT decoding to ofdata_to_platdata()Simon Glass2016-07-14-38/+64
| | | | | | | | | | | | | | | | | | It is more correct to avoid touching the device tree in the probe() method. Update the driver to work this way. Note that only SPL needs to fiddle with the SDRAM registers, so decoding the platform data fully is not necessary in U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: syscon: Update to work with of-platdataSimon Glass2016-07-14-0/+38
| | | | | | | | | | | | | | | | | | The syscon devices all end up having diffent driver names with of-platdata, since the driver name comes from the first string in the compatible list. Add separate device declarations for each one, and add a bind method to set up driver_data correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Don't use spl_boot_device() with of-platdataSimon Glass2016-07-14-0/+2
| | | | | | | | | | | | | | This function cannot look at the device tree when of-platdata is used. Update the code to handle this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Move the MMC setup check earlierSimon Glass2016-07-14-11/+12
| | | | | | | | | | | | | | When the boot ROM sets up MMC we don't need to do it again. Remove the MMC setup code entirely. Signed-off-by: Simon Glass <sjg@chromium.org>
| * rockchip: Update the sdram-channel property to support of-platdataSimon Glass2016-07-14-1/+8
| | | | | | | | | | | | | | Add an extra byte so that this data is not byteswapped. Add a comment to the code to explain the purpose. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Add a test device that uses of-platdataSimon Glass2016-07-14-0/+48
| | | | | | | | | | | | | | | | | | | | Start up the test devices. These print out of-platdata contents, providing a check that the of-platdata feature is working correctly. The device-tree changes are made to sandbox.dts rather than test.dts. since the former controls the of-platdata generation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Add a new sandbox_spl boardSimon Glass2016-07-14-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | It is useful to be able to build SPL for sandbox. It provides additional build coverage and allows SPL features to be tested in sandbox. However it does not need worthwhile to always create an SPL build. It nearly doubles the build time and the feature is (so far) seldom used. So for now, create a separate build target for sandbox SPL. This allows experimentation with this new feature without impacting existing workflows. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Add basic SPL implementationSimon Glass2016-07-14-0/+75
| | | | | | | | | | | | | | Add an sandbox implementation for the generic SPL framework. This supports locating and running U-Boot proper. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Don't include the main loop in SPLSimon Glass2016-07-14-0/+2
| | | | | | | | | | | | | | SPL does not have a command interface so we should not include the main loop code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Don't use PCI in SPLSimon Glass2016-07-14-1/+3
| | | | | | | | | | | | PCI is not supported in SPL for sandbox, so avoid using it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Add some missing headers in cpu.cSimon Glass2016-07-14-0/+2
| | | | | | | | | | | | These headers are needed in case they are not transitively included. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Correct header file order in cpu.cSimon Glass2016-07-14-1/+1
| | | | | | | | | | | | The dm/ file should go at the end. Move it. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Support building an SPL imageSimon Glass2016-07-14-0/+5
| | | | | | | | | | | | | | When building an SPL image, override the link flags so that it uses the system libraries. This is similar to the way the non-SPL image is built. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Allow chaining from SPL to U-Boot properSimon Glass2016-07-14-0/+51
| | | | | | | | | | | | | | | | SPL is expected to load and run U-Boot. This needs to work with sandbox also. Provide a function to locate the U-Boot image, and another to start it. This allows SPL to function on sandbox as it does on other archs. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Show cache warnings in U-Boot proper onlySimon Glass2016-07-14-2/+2
| | | | | | | | | | | | Avoid bloating the SPL image size. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Don't invalidate unaligned cache regionsSimon Glass2016-07-14-21/+2
| | | | | | | | | | | | | | | | | | At present armv7 will unhappily invalidate a cache region and print an error message. Make it skip the operation instead, as it does with other cache operations. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
* | arm: Move check_cache_range() into a common placeSimon Glass2016-07-14-51/+24
| | | | | | | | | | | | | | This code is common, so move it into a common file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
* | ARM: OMAP5+: Enable errata i727Lokesh Vutla2016-07-14-3/+3
| | | | | | | | | | | | | | | | Errata i727 is applicable on all OMAP5 and DRA7 variants but enabled only on OMAP5 ES1.0. So, enable it on all platforms. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | stm32: Change USART port to USART6 for stm32f746 discovery boardToshifumi NISHINAGA2016-07-14-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | This change is to remove a halt at about 200KiB while sending a large(1MiB) binary to a micro controller using USART1. USART1 is connected to a PC via an on-board ST-Link debugger that also functions as a USB-Serial converter. However, it seems to loss some data occasionally. So I changed the serial port to USART6 and connected it to the PC using an FTDI USB-Serial cable, therefore the transmission was successfully completed. Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
* | stm32: Add SDRAM support for stm32f746 discovery boardToshifumi NISHINAGA2016-07-14-1/+136
| | | | | | | | | | | | | | | | | | | | This patch adds SDRAM support for stm32f746 discovery board. This patch depends on previous patch. This patch is based on STM32F4 and emcraft's[1]. [1]: https://github.com/EmcraftSystems/u-boot Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
* | stm32: clk: Add 200MHz clock configuration for stm32f746 discovery boardToshifumi NISHINAGA2016-07-14-1/+302
| | | | | | | | | | | | | | | | | | This patch adds 200MHz clock configuration for stm32f746 discovery board. This patch is based on STM32F4 and emcraft's[1]. [1]: https://github.com/EmcraftSystems/u-boot Signed-off-by: Toshifumi NISHINAGA <tnishinaga.dev@gmail.com>
* | sandbox: Don't exit when bootm completesSimon Glass2016-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present sandbox exits when the 'bootm' command completes, since it is not actually able to run the OS that is loaded. Normally 'bootm' failure is considered a fatal error in U-Boot. However this is annoying for tests, which may want to examine the state after a test is complete. In any case there is a 'reset' command which can be used to exit, if required. Change the behaviour to return normally from the 'bootm' command on sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Teddy Reed <teddy.reed@gmail.com>
* | linux/io.h: add generic ioremap()/iounmap() definesMasahiro Yamada2016-07-14-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For most of architectures in U-Boot, virtual address is straight mapped to physical address. So, it makes sense to have generic defines of ioremap and friends in <linux/io.h>. All of them are just empty and will disappear at compile time, but they will be helpful to implement drivers which are counterparts of Linux ones. I notice MIPS already has its own implementation, so I added a Kconfig symbol CONFIG_HAVE_ARCH_IOREMAP which MIPS (and maybe Sandbox as well) can select. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | arm, nds32, sh: remove useless ioremap()/iounmap() definesMasahiro Yamada2016-07-14-101/+0
| | | | | | | | | | | | | | These defines are valid only when iomem_valid_addr is defined, but I do not see such defines anywhere. Remove. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | types.h: move and redefine resource_size_tMasahiro Yamada2016-07-14-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, this is only defined in arch/arm/include/asm/types.h, so move it to include/linux/types.h to make it available for all architectures. I defined it with phys_addr_t as Linux does. I needed to surround the define with #ifdef __KERNEL__ ... #endif to avoid build errors in tools building. (Host tools should not include <linux/types.h> in the first place, but this is already messy in U-Boot...) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm: am4x: add U-Boot FIT signing and SPL image post-processingMadan Srinivas2016-07-14-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the SPL build procedure for AM437x high-security (HS) device variants to create a secure u-boot_HS.img FIT blob that contains U-Boot and DTB artifacts signed (and optionally encrypted) with a TI-specific process based on the CONFIG_TI_SECURE_DEVICE config option and the externally-provided image signing tool. Also populate the corresponding FIT image post processing call to be performed during SPL runtime. Signed-off-by: Madan Srinivas <madans@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: omap5: add U-Boot FIT signing and SPL image post-processingAndreas Dannenberg2016-07-14-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the SPL build procedure for AM57xx and DRA7xx high-security (HS) device variants to create a secure u-boot_HS.img FIT blob that contains U-Boot and DTB artifacts signed with a TI-specific process based on the CONFIG_TI_SECURE_DEVICE config option and the externally-provided image signing tool. Also populate the corresponding FIT image post processing call to be performed during SPL runtime. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: omap-common: Update to generate secure U-Boot FIT blobAndreas Dannenberg2016-07-14-14/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds commands so that when a secure device is in use and the SPL is built to load a FIT image (with combined U-Boot binary and various DTBs), these components that get fed into the FIT are all processed to be signed/encrypted/etc. as per the operations performed by the secure-binary-image.sh script of the TI SECDEV package. Furthermore, perform minor comments cleanup to make better use of the available space. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm: omap-common: secure ROM signature verify APIAndreas Dannenberg2016-07-14-0/+97
| | | | | | | | | | | | | | | | | | | | | | Adds an API that verifies a signature attached to an image (binary blob). This API is basically a entry to a secure ROM service provided by the device and accessed via an SMC call, using a particular calling convention. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: omap-common: add secure rom call API for secure devicesAndreas Dannenberg2016-07-14-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | Adds a generic C-callable API for making secure ROM calls on OMAP and OMAP-compatible devices. This API provides the important function of flushing the ROM call arguments to memory from the cache, so that the secure world will have a coherent view of those arguments. Then is simply calls the omap_smc_sec routine. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: omap-common: add secure smc entryDaniel Allred2016-07-14-9/+42
| | | | | | | | | | | | | | | | | | | | | | Add an interface for calling secure ROM APIs across a range of OMAP and OMAP compatible high-security (HS) device variants. While at it, also perform minor cleanup/alignment without any change in functionality. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm: cache: add missing dummy functions for when dcache disabledDaniel Allred2016-07-14-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Adds missing flush_dcache_range and invalidate_dcache_range dummy (empty) placeholder functions to the #else portion of the #ifndef CONFIG_SYS_DCACHE_OFF, where full implementations of these functions are defined. Signed-off-by: Daniel Allred <d-allred@ti.com> Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | arm64: add better and more generic spin-table supportMasahiro Yamada2016-07-14-4/+134
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two enable methods supported by ARM64 Linux; psci and spin-table. The latter is simpler and helpful for quick SoC bring up. My main motivation for this patch is to improve the spin-table support, which allows us to boot an ARMv8 system without the ARM Trusted Firmware. Currently, we have multi-entry code in arch/arm/cpu/armv8/start.S and the spin-table is supported in a really ad-hoc way, and I see some problems: - We must hard-code CPU_RELEASE_ADDR so that it matches the "cpu-release-addr" property in the DT that comes from the kernel tree. - The Documentation/arm64/booting.txt in Linux requires that the release address must be zero-initialized, but it is not cared by the common code in U-Boot. We must do it in a board function. - There is no systematic way to protect the spin-table code from the kernel. We are supposed to do it in a board specific manner, but it is difficult to predict where the spin-table code will be located after the relocation. So, it also makes difficult to hard-code /memreserve/ in the DT of the kernel. So, here is a patch to solve those problems; the DT is run-time modified to reserve the spin-table code (+ cpu-release-addr). Also, the "cpu-release-addr" property is set to an appropriate address after the relocation, which means we no longer need the hard-coded CPU_RELEASE_ADDR. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Revert "armv8: Enable CPUECTLR.SMPEN for coherency"Tom Rini2016-07-14-8/+0
| | | | | | | | | Upon further review this breaks most other platforms as we need to check what core we're running on before touching it at all. This reverts commit d73718f3236c520a92efa401084c658e6cc067f3. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-07-12-13/+474
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| * x86: link: Correct a failure in DRAM initSimon Glass2016-07-12-0/+5
| | | | | | | | | | | | | | | | | | | | With the change to set up pinctrl after relocation, link fails to boot. Add a special case in the link code to handle this. Fixes: d8906c1f (x86: Probe pinctrl driver in cpu_init_r()) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add Advantech SOM-DB5800/SOM-6867 supportGeorge McCollister2016-07-12-1/+295
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Advantech SOM-DB5800 with the SOM-6867 installed. This is very similar to conga-qeval20-qa3-e3845 in that there is a reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867) installed. Currently supported: - 2x UART (From ITE EC on SOM-6867) routed to COM3/4 connectors on SOM-DB5800. - 4x USB 2.0 (EHCI) - Video - SATA - Ethernet - PCIe - Realtek ALC892 HD Audio Pad configuration for HDA_RSTB, HDA_SYNC, HDA_CLK, HDA_SDO HDA_SDI0 is set in DT to enable HD Audio codec. Pin defaults for codec pin complexs are not changed. Not supported: - Winbond Super I/O (Must be disabled with jumpers on SOM-DB8500) - USB 3.0 (XHCI) - TPM Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: baytrail: acpi: Hide internal UART per GNVS settingBin Meng2016-07-12-11/+8
| | | | | | | | | | | | | | | | | | | | If global NVS says internal UART is not enabled, hide it in the ASL code so that OS won't see it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: acpi: Pack global NVS into ACPI tableBin Meng2016-07-12-0/+32
| | | | | | | | | | | | | | | | | | | | Now that platform-specific ACPI global NVS is added, pack it into ACPI table and get its address fixed up. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Introduce ACPI global NVSBin Meng2016-07-12-0/+41
| | | | | | | | | | | | | | | | This introduces quark-specific ACPI global NVS structure, defined in both C header file and ASL file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Introduce ACPI global NVSBin Meng2016-07-12-0/+81
| | | | | | | | | | | | | | | | | | | | This introduces baytrail-specific ACPI global NVS structure, defined in both C header file and ASL file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: George McCollister <george.mccollister@gmail.com> Tested-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Wrap setup_internal_uart() call with CONFIG_INTERNAL_UARTBin Meng2016-07-12-1/+1
| | | | | | | | | | | | | | | | | | | | For any FSP-enabled boards that want to enable debug UART support, setup_internal_uart() will be called, but this API is only available on BayTrail platform. Change to wrap it with CONFIG_INTERNAL_UART. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Introduce a Kconfig option for the internal UARTBin Meng2016-07-12-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | There are quite a number of BayTrail boards that uses an external SuperIO chipset to provide the legacy UART. For such cases, it's better to have a Kconfig option to enable the internal UART. So far BayleyBay and MinnowMax boards are using internal UART as the U-Boot console, enable this on these two boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2016-07-11-11/+143
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| * | ARM: dts: dra7x: Support QSPI MODE-0 operation at 64MHzVignesh R2016-07-09-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to Data Manual(SPRS915P) of AM57x, TI QSPI controller on DRA74(rev 1.1+)/DRA72 EVM can support up to 64MHz in MODE-0, whereas MODE-3 is limited to 48MHz. Hence, switch to MODE-0 for better throughput. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: K2G: Add support for QSPI controllerVignesh R2016-07-09-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | K2G SoC has a Cadence QSPI controller to communicate with NOR flash devices. Add DT nodes to support the same. Also, K2G EVM has a s25fl512s flash connect to QSPI bus at CS 0. Add nor flash slave node for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2g: add support for Davinci SPI controllerVignesh R2016-07-09-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | K2G SoC has 4 SPI instances that are compatible with davinci_spi controller(present on previous generation of Keystone2 devices). Add DT nodes for the same. K2G EVM has a N25Q128A13 SPI NOR flash connected on SPI-1. Add DT bindings for the same. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * | ARM: dts: k2l: Enable Davinci SPI controllerVignesh R2016-07-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that davinci_spi driver has been converted to DM framework, enable the same in DT. Also add "spi-flash" as compatible property to n25q128a11 node as it is required for flash device to be probed in U-Boot. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
generated by cgit v1.1 at 2024-11-15 01:43:13 +0000