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* Merge branch 'u-boot-pxa/master' into 'u-boot-arm/master'Albert ARIBAUD2013-05-11-545/+374
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| * pxa: Add weak attribute to reset_cpu() functionŁukasz Dałek2013-05-05-1/+1
| | | | | | | | | | | | | | This commit allows pxa2xx based boards to reimplement reset_cpu() function with board specific reset sequence. Signed-off-by: Lukasz Dalek <luk0104@gmail.com>
| * pxa27x_udc: remove call to unimplemented set_GPIO_mode()Mike Dunn2013-05-05-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_USB_DEV_PULLUP_GPIO is defined, a link error occurs because the set_GPIO_mode() helper function is not implemented. This function doesn't do much except make the code a little more readable, so I just manually coded its equivalent and removed the prototype from the header file. It is invoked no where else in the code. While I was at it, I noticed that two other function prototypes in the same header file are also neither implemented nor invoked anywhere, so I removed them as well. Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
| * Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-05-02-45/+109
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| | * powerpc/mpc85xx: Changed LIODN offset valuesCristian Sovaiala2013-05-02-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extending LIODN offset range from 1-5 to 1-10 While using a qman portal with a higher index the LIODN offset is incorrectly set, thus extending the range of offsets covers all 10 qman portals Signed-off-by: Cristian Sovaiala <cristian.sovaiala@freescale.com> Acked-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Extend workaround for erratum DDR_A003 to other SoCsYork Sun2013-05-02-0/+3
| | | | | | | | | | | | | | | | | | | | | Erratum DDR_A003 applies to P5020, P3041, P4080, P3060, P2041, P5040. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/85xx: add SerDes bank 4 lanesTimur Tabi2013-05-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Only some chips have four SerDes banks, so don't define lanes for a bank that doesn't exist. Signed-off-by: Timur Tabi <timur@tabi.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx:IFC Errata A003399 is not valid for BSC913xPrabhakar Kushwaha2013-05-02-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | As per Errata list of BSC9131 and BSC9132, IFC Errata A003399 is no more valid. So donot compile its workaround. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * mpc85xx: Fix a compiler warning when CONFIG_WATCHDOG is turned onHorst Kronstorfer2013-05-02-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | cpu.c:288:2: warning: implicit declaration of function 'reset_85xx_watchdog' [-Wimplicit-function-declaration] Signed-off-by: Horst Kronstorfer <hkronsto@frequentis.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/85xx: Add workaround for errata USB-14 (enable on P204x/P3041/P50x0)Xulei2013-05-02-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * fman/mEMAC: set SETSP bit in IF_MODE regisgter for RGMII speedZang Roy-R619112013-05-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some legacy RGMII phys don't have in band signaling for the speed information. so set the RGMII MAC mode according to the speed got from PHY. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Reported-by: John Traill <john.traill@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: set clock-frequency for T4/B4 clockgen nodeTang Yuantian2013-05-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | For T4/B4, the clockgen node compatible string is updated to version 2. Add clock-frequency setting for this new version. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/b4860: Adding workaround errata A-005871Shengzhou Liu2013-05-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Per the latest errata updated, B4860/B4420 Rev 1.0 has also errata A-005871, so adding define A-005871 for B4 SoCs. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/b4: Fix the wrong register offset of B4 PCIE moduleLiu Gang2013-05-02-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4420/B4860 PCIE can not work because of the wrong definition of the PCIE register offset in the file: arch/powerpc/include/asm/immap_85xx.h Add the judgement of B4420/B4860 to make the register offset to: #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: add setting of clock-frequency for mpic nodeDongsheng.wang@freescale.com2013-05-02-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Set the device tree property associated with the mpic source frequency. The frequency is used for mpic timer. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * powerpc/mpc85xx: Add revision properties in portal device tree node 'pme'Jeffrey Ladouceur2013-05-02-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'fsl,pme-rev1' and 'fsl-pme-rev2' properties have been added to the pme portal node. This is required for software to determine which version of PME hardware is present and take appropriate actions. These properties are a direct reflection of the corresponding ccsr pme register value. Also removed unnecessary static global variables. Signed-off-by: Jeffrey Ladouceur <Jeffrey.Ladouceur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxTom Rini2013-05-02-6/+0
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| | * mpc512x: remove dead codeAnatolij Gustschin2013-05-02-6/+0
| | | | | | | | | | | | | | | | | | | | | The prt_mpc512x_clks() function isn't referenced anywhere and its prototype is wrong. Remove it. Signed-off-by: Anatolij Gustschin <agust@denx.de>
| * | lib: consolidate hang()Andreas Bießmann2013-05-01-124/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Delete all occurrences of hang() and provide a generic function. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> [trini: Modify check around puts() in hang.c slightly] Signed-off-by: Tom Rini <trini@ti.com>
| * | nios2: fix style in board.c.Andreas Bießmann2013-05-01-22/+21
| | | | | | | | | | | | | | | | | | Make nios2's board.c checkpatch clean. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | microblaze: fix style in board.cAndreas Bießmann2013-05-01-32/+31
| |/ | | | | | | | | | | | | | | Make microblaze's board.c checkpatch clean. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Reviewed-by: Michal Simek <monstr@monstr.eu>
| * sandbox: Allow -c argument to provide a command listSimon Glass2013-05-01-1/+1
| | | | | | | | | | | | | | | | This allows passing of entire scripts to sandbox with the -c argument, which is useful for testing. Commands can be delimited with a newline or semicolon. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Add CONFIG_OF_HOSTFILE to read FDT from host fileSimon Glass2013-05-01-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | With sandbox it is tricky to add an FDT to the image at build time (or later) since we build an ELF file, not a plain binary, and the address space of the whole U-Boot is not accessible in the emulated memory map of sandbox. Sandbox can read files directly from the host, though, so add an option to read an FDT from a host file on start-up. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Switch over to generic boardSimon Glass2013-05-01-307/+11
| | | | | | | | | | | | | | | | | | Add generic board support for sandbox. and remove the old board init code. Select CONFIG_SYS_GENERIC_BOARD for sandbox now that this is supported. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@ti.com>
| * sandbox: Provide a way to map from host RAM to U-Boot RAMSimon Glass2013-05-01-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In many cases, pointers to memory are passed around, and these pointers refer to U-Boot memory, not host memory. This in itself is not a problem. However, in a few places, we cast that pointer back to a ulong (being a U-Boot memory address). It is possible to convert many of these cases to avoid this. However there are data structures (e.g. struct bootm_headers) which use pointers. We could with a lot of effort adjust the structs and all code that uses them to use ulong instead of pointers. This seems like an unacceptable cost, since our objective with sandbox is to minimise the impact on U-Boot code while maximising the features available to sandbox. Therefore, create a map_to_sysmem() function which converts from a pointer to a U-Boot address. This can be used sparingly when needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * Merge branch 'microblaze' of git://www.denx.de/git/u-boot-microblazeTom Rini2013-05-01-0/+7
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| | * watchdog: Add support for Xilinx Microblaze watchdogMichal Simek2013-04-30-0/+7
| | | | | | | | | | | | | | | | | | | | | Watchdog can be used on Microblaze, PPC and Zynq hw designs. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
| * | ppc4xx: Add SPL supportStefan Roese2013-04-22-4/+185
| |/ | | | | | | | | | | | | | | | | | | This patch adds SPL booting support (NOR flash) for the PPC4xx platforms. This SPL booting (Falcon mode) will be used by the upcoming lcd4_lwmon5 board port (lwmon5 variant). Signed-off-by: Stefan Roese <sr@denx.de>
* | fpga: zynq: Add support for loading bitstreamMichal Simek2013-05-06-2/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | Devcfg device requires to load bitstream in binary format. But u-boot also has an option for loading bitstream in bit format. Let's handle both cases by zynqpl driver. Also add suport for loading partial bitstreams. The first driver version was done by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | i2c: zynq: Add support for Xilinx ZynqMichal Simek2013-04-30-0/+2
| | | | | | | | | | | | | | | | | | Support Xilinx Zynq i2c controller. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Tom Rini <trini@ti.com>
* | mmc: Add support for Xilinx Zynq sdhci controllerMichal Simek2013-04-30-0/+5
| | | | | | | | | | | | | | Add support for SD, MMC and eMMC card on Xilinx Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | zynq: Move macros to hardware.hMichal Simek2013-04-30-0/+2
| | | | | | | | | | | | | | | | Add all fixed addresses to hardware.h and change petalinux configuration to support this. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | net: gem: Fix gem driver on 1Gbps LANMichal Simek2013-04-30-1/+33
| | | | | | | | | | | | | | | | | | | | The whole driver used 100Mbps because of zc702 rev B. Fix problem with not setup proper clock for gem1. This is generic approach for clk setup. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | zynq: Move scutimer baseaddr to hardware.hMichal Simek2013-04-30-1/+3
| | | | | | | | | | | | | | | | Move baseaddr to hardware.h to be shared between configurations. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | arm: zynq: Rename XPSS_ prefix to ZYNQ_ for hardcoded SoC addressesMichal Simek2013-04-30-6/+6
| | | | | | | | | | | | | | | | XPSS prefix was used in past and it is obsolete for quite some time. Let's use correct SoC name which is Zynq. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* | arm: zynq: U-Boot udelay < 1000 FIXDavid Andrey2013-04-30-9/+37
|/ | | | | | | | | Rework the __udelay function of U-Boot Zynq Arch to handle delay < 1000 usec Signed-off-by: David Andrey <david.andrey@netmodule.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@ti.com>
* Merge branch 'master' of git://git.denx.de/u-boot-arm into HEADTom Rini2013-04-18-55/+221
|\ | | | | | | | | | | | | | | | | | | Quick manual fixup to merge the USB boot related defines and TPM related defines. Conflicts: include/configs/exynos5250-dt.h Signed-off-by: Tom Rini <trini@ti.com>
| * exynos: Correct use of 64-bit divisionSimon Glass2013-04-17-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The current code is causing errors like this on my toolchains: /usr/x86_64-pc-linux-gnu/armv7a-cros-linux-gnueabi/binutils-bin/2.22/ ld.bfd.real: failed to merge target specific data of file /usr/lib/gcc/ armv7a-cros-linux-gnueabi/4.7.x-google/libgcc.a(_divdi3.o) Use do_div() to avoid this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * Tegra: Split tegra_get_chip_type() into soc & sku funcsTom Warren2013-04-15-36/+83
| | | | | | | | | | | | | | | | | | | | | | As suggested by Stephen Warren, use tegra_get_chip() to return the pure CHIPID for a Tegra SoC (i.e. 0x20 for Tegra20, 0x30 for Tegra30, etc.) and rename tegra_get_chip_type() to reflect its true function, i.e. tegra_get_chip_sku(), which returns an ID like TEGRA_SOC_T25, TEGRA_SOC_T33, etc. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra: Fix MSELECT clock divisors for T30/T114.Tom Warren2013-04-15-8/+6
| | | | | | | | | | | | | | | | | | A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra114: Initialize System Counter (TSC) with osc frequencyTom Warren2013-04-15-0/+72
| | | | | | | | | | | | | | | | | | T114 needs the SYSCTR0 counter initialized so the TSC can be read by the kernel. Do it in the bootloader since it's a write-once deal (secure/non-secure mode dependent). Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
| * Tegra: Configure L2 cache control reg properly.Tom Warren2013-04-15-8/+52
| | | | | | | | | | | | | | | | | | | | Without this change, kernel fails at calling function cache_clean_flush during kernel early boot. Aprocryphally, intended for T114 only, so I check for a T114 SoC. Works (i.e. dalmore 3.8 kernel now starts printing to console). Signed-off-by: Tom Warren <twarren@nvidia.com>
| * Tegra: Restore cp15 VBAR _start vector write for ARMv7Tom Warren2013-04-15-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | A start vector fix was added by AneeshV for OMAP4 (commit 0d479b53), and caused the old monilithic Tegra builds to hang due to an undefined instruction trap. Previously, the code needed to run on both the AVP (ARM7TDI) and A9, and the AVP doesn't have a CP15 register. I corrected this in commit 6d6c0bae w/#ifndef CONFIG_TEGRA, but now that we use SPL, and boot the AVP w/o any ARMv7 code, I can revert my change, and make Aneesh's change apply to Tegra. Signed-off-by: Tom Warren <twarren@nvidia.com>
| * ARM: tegra: support T33 SKU of Tegra30Stephen Warren2013-04-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make U-Boot aware of the T33 SKU of Tegra30, and treat it identically to any other Tegra30. An alternative would be to simply remove the SKU checking from tegra_get_chip_type(); most use of the value most likely simply wants to know the current chip, not the specific SKU. Or, the function could be split into separate tegra_get_chip() and tegra_get_sku() for the cases where differentiation really is required. I wonder whether tegra_get_chip_type() should printf() whenever any unkown chip/SKU is found, although perhaps the function is called so early that the printf() wouldn't actually make it to the UART anyway. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2013-04-16-1/+6
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| * x86: Fix DRAM bank size init with generic boardSimon Glass2013-04-15-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | The intention of the memory init code is that it should work the same with CONFIG_SYS_GENERIC_BOARD and without. This is tricky because dram_init() is called prior to relocation with generic board (matching other archs) and after relocation without generic board. Adjust the init sequence so that dram_init() is not called in the generic board case, which seems like the easiest fix for now. Also ensure that relocation addresses are still calculated. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARMv7: start.S: stay in HYP mode if u-boot is entered in itAndre Przywara2013-04-15-3/+7
|/ | | | | | | | | | The KVM and Xen hypervisors for the Cortex-A15 virtualization implementation need to be entered in HYP mode. Should the primary board firmware already enter HYP mode (Calxeda firmware does that), we should not deliberately drop back to SVC mode. Since U-boot does not use the MMU, running in HYP mode is just fine. Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
* ARM: fix CONFIG_SPL_MAX_SIZE semanticsAlbert ARIBAUD2013-04-14-15/+13
| | | | | | | | | | | | | | | | | | | | Remove SPL-related ASSERT() in arch/arm/cpu/u-boot.lds as this file is never used for SPL builds. Rewrite the ASSERT() in arch/arm/cpu/u-boot-spl.lds to separately test image (text,data,rodata...) size, BSS size, and full footprint each against its own max, and make Tegra boards check full footprint. Also, output section mmutable is not used in SPL builds. Remove it. Finally, update README regarding the (now homogeneous) semantics of CONFIG_SPL_[BSS_]MAX_SIZE and add the new CONFIG_SPL_MAX_FOOTPRINT macro. Signed-off-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Reported-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
* Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'Albert ARIBAUD2013-04-14-0/+2
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| * spi: mxc_spi: Set master mode for all channelsFabio Estevam2013-04-13-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The glitch in the SPI clock line, which commit 3cea335c34 (spi: mxc_spi: Fix spi clock glitch durant reset) solved, is back now and itwas re-introduced by commit d36b39bf0d (spi: mxc_spi: Fix ECSPI reset handling). Actually the glitch is happening due to always toggling between slave mode and master mode by configuring the CHANNEL_MODE bits in this reset function. Since the spi driver only supports master mode, set the mode for all channels always to master mode in order to have a stable, "glitch-free" SPI clock line. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
generated by cgit v1.1 at 2024-11-20 17:13:08 +0000