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* nios2: set up the debug UART earlyThomas Chou2016-02-06-0/+7
| | | | | | | Set up the debug UART early if enabled, so that it is ready to use. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
* imx: mx6: implement mmc_get_env_devPeng Fan2016-02-04-0/+32
| | | | | | | | | | Implement mmc_get_env_dev, devno can be got from smbr1 of SRC. Introduce a weak function board_mmc_get_env_dev, different boards can implement it according to different sdhc controllers that used by the board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* imx: mx7dsabresd: move mmc_get_env_devno to soc codePeng Fan2016-02-04-0/+21
| | | | | | | | | | | Move mmc_get_env_devno to soc.c and rename to mmc_get_env_dev to match the one in common/env_mmc.c. Introduce a weak function board_mmc_get_env_dev. Different boards can implement this according to sdhc controller which is used by the board. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
* arm: pcm052: Add device tree file'sBhuvanchandra DV2016-02-02-1/+24
| | | | | | | | | - Add device tree files for Phytec phyCORE-Vybrid Board. - Enable lpuart support for Phytec phyCORE-Vybrid Board. - Use UART1 for stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: vf610-twr: Add device tree file'sBhuvanchandra DV2016-02-02-1/+24
| | | | | | | | | - Add device tree files for NXP/Freescale VF610 Tower Board. - Enable lpuart support on NXP/Freescale VF610 Tower Board. - Use UART1 as stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: colibri-vf: Enable serial supportBhuvanchandra DV2016-02-02-0/+10
| | | | | | | | - Enable lpuart support on Toradex Colibri VF50/VF61 - Use UART0 for stdout. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: vybrid: Update the license stringBhuvanchandra DV2016-02-02-20/+0
| | | | | | | | Since SPDX license is already there, drop the full one. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* arm: vybrid: Enable lpuart supportBhuvanchandra DV2016-02-02-0/+43
| | | | | | | | Add device tree node's for lpuart on Vybrid platform Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Acked-by: Stefan Agner <stefan.agner@toradex.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* imx: mx6ul/sx: Fix issue in LCDIF clock dividers calculationYe Li2016-02-02-4/+0
| | | | | | | | | | The checking with max frequency supported is not correct, because the temp is calculated by max pre and post dividers. We can decrease any divider to meet the max frequency limitation. Actually, the calculation below the codes is doing this way to find best pre and post dividers. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6sx: Fix issue in LCDIF clock enablementYe Li2016-02-02-2/+2
| | | | | | | | Wrong checking for the base_addr paramter with LCDIF1 and LCDIF2. Always enter the -EINVAL return. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* imx: mx6sxsabreauto: Add support for mx6sx SABREAUTO boardYe Li2016-02-02-0/+6
| | | | | | | Initial version for mx6sx SABREAUTO board support with features: PMIC, QSPI, NAND flash, SD/MMC, USB, Ethernet, I2C, IO Expander. Signed-off-by: Ye Li <ye.li@nxp.com>
* mx6: soc: Add ENET2 mac address supportYe Li2016-02-02-29/+26
| | | | | | | The i.MX6SX and i.MX6UL has two ENET controllers, add support for reading MAC address from fuse for ENET2. Signed-off-by: Ye Li <ye.li@nxp.com>
* arm: imx6: Add DDR3 calibration code for MX6 Q/D/DLMarek Vasut2016-02-02-0/+564
| | | | | | | | | Add DDR3 calibration code for i.MX6Q, i.MX6D and i.MX6DL. This code fine-tunes the behavior of the MMDC controller in order to improve the signal integrity and memory stability. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-02-02-14/+221
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| * board: atmel: sama5d2_xplained: add SPL supportWenyou Yang2016-02-02-0/+34
| | | | | | | | | | | | | | | | The sama5d2 Xplained SPL supports the boot medias: spi flash and SD Card. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: mpddrc: use IP version to check configurationWenyou Yang2016-02-02-7/+11
| | | | | | | | | | | | | | | | To remove the unnecessary #ifdef-endif, use the mpddrc IP version to check whether or not the interleaved decoding type is supported. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: mpddrc: add mpddrc DDR3-SDRAM initializationWenyou Yang2016-02-02-8/+167
| | | | | | | | | | | | | | | | | | | | | | | | The DDR3-SDRAM initialization sequence is implemented in accordance with the DDR3-SRAM/DDR3L-SDRAM initialization section described in the SAMA5D2 datasheet. Add registers and definitions of mpddrc controller, which is used to support DDR3 devices. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * arm: at91/spl: mpddrc: add struct atmel_mpddrc_configWenyou Yang2016-02-02-2/+12
| | | | | | | | | | | | | | | | | | | | Add struct atmel_mpddrc_config to accommodate the mpddrc register configurations, not using the mpddrc register map structure, struct atmel_mpddrc, in order to increase readability and reduce run-time memory use. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-02-02-0/+71
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| * | arm8: ls2080: Move the core errata defines out of board specific fileAshish kumar2016-02-01-0/+2
| | | | | | | | | | | | | | | | | | | | | Valid for core A57 Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080a: Implement workaround for core errata 829520, 833471Ashish kumar2016-02-01-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 829520: Code bounded by indirect conditional branch might corrupt instruction stream. Workaround: Set CPUACTLR_EL1[4] = 1'b1 to disable the Indirect Predictor. 833471: VMSR FPSCR functional failure or deadlock. Workaround: Set CPUACTLR[38] to 1, which forces FPSCR write flush. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043aqds: fix DSPI/QSPI node in dts fileQianyu Gong2016-02-01-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the lost dts info when merging patches. Fix DSPI node for 'commit e0579a5852b3 ("armv8/ls1043aqds: add DSPI support")' and QSPI node for 'commit 166ef1e90ce4 ("armv8/ls1043aqds: add QSPI support in SD boot")'. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-02-01-80/+662
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| * | | board: Enable ethernet, tftpboot support to pic32mzdask board.Purna Chandra Mandal2016-02-01-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds ethernet, TFTP support for PIC32MZ[DA] Starter Kit. Also custom environment variables/scripts are added to help boot from network. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
| * | | board: add SDHCI support for PIC32MZDASK board.Purna Chandra Mandal2016-02-01-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable MMC, SDHCI, FAT_FS support for PIC32MZ[DA] StarterKit. Also add custom scripts, rules to boot Linux from microSD card. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
| * | | board: Add Microchip PIC32MZ[DA]-Starter-Kit board.Purna Chandra Mandal2016-02-01-1/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for Microchip PIC32MZ[DA] StarterKit board based on a PIC32MZ[DA] family of microcontroller. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | MIPS: Add support for Microchip PIC32MZ[DA] SoC family.Purna Chandra Mandal2016-02-01-2/+379
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Microchip PIC32MZ[DA] SoC family support. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal2016-02-01-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver initializes PIC32 DDR2 SDRAM controller and internal DDR2 Phy module. DDR2 controller operates in half-rate mode (upto 533MHZ frequency). Signed-off-by: Paul Thacker <paul.thacker@microchip.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | MIPS: initial infrastructure for Microchip PIC32 architecturePurna Chandra Mandal2016-02-01-0/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create initial directory, Kconfigs needed for PIC32 architecture support. Also add PIC32 specific register definition required for drivers. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * | | MIPS: Support dynamic I/O port base addressPaul Burton2016-02-01-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing mips_io_port_base variable isn't suitable for use early during boot since it will be stored in the .data section which may not be writable pre-relocation. Fix this by moving the I/O port base address into struct arch_global_data. In order to avoid adding this field for all targets, make this dependant upon a new Kconfig entry CONFIG_DYNAMIC_IO_PORT_BASE. Malta is the only board which sets a non-zero I/O port base, so select this option only for Malta. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | | MIPS: Remove SLOW_DOWN_IOPaul Burton2016-02-01-37/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONF_SLOWDOWN_IO is never set for any target, so remove the dead code in the SLOW_DOWN_IO macro. This is done in preparation for changes to mips_io_port_base which can be avoided in this path by removing it entirely. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * | | mips: cache: Bulletproof the code against cornercasesMarek Vasut2016-02-01-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes sure that the flush/invalidate_dcache_range() functions can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0); This call is valid and is happily produced by USB EHCI code for example. The expected behavior of the cache function(s) in this case is that they will do no operation, since the size is zero. The current implementation though has a problem where such invocation will result in a hard CPU hang. This is because under such conditions, where the start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop will then try to iterate over the entire address space, which in itself is wrong. But iterating over the entire address space might also hit some odd address which will cause bus hang. The later happens on the Atheros MIPS. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Hans de Goede <hdegoede@redhat.com>
| * | | MIPS: start.S: fix and optimize instructionsDaniel Schwierzeck2016-02-01-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix 32 vs 64 bit load/store instructions. Access CP0_WATCHHI as 32 Bit register. Use 64 Bit register access for clearing gd_data and copying U-Boot. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | MIPS: initialize board_init_f() argument to zero.Purna Chandra Mandal2016-02-01-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | Argument boot_flags of board_init_f() should be set to 0 as $a0 may be utilized in lowlevel_init() or mips_cache_reset() or previous stage boot-loader. Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | arm: config: enforce -fno-pic for gccPeng Fan2016-01-31-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Android's tool chain enable the -mandroid at default. This option will enable the -fpic, which cause uboot compilation failure: " LD u-boot u-boot contains unexpected relocations: R_ARM_ABS32 R_ARM_RELATIVE " In my testcase, arm-linux-androideabi-gcc-4.9 internally enables '-fpic', so when compiling code, there will be relocation entries using type R_ARM_GOT_BREL and .got section. When linking all the built-in.o using ld, there will be R_ARM_ABS32 relocation entry and .got section in the final u-boot elf image. This can not be handled by u-boot, since u-boot only expects R_ARM_RELATIVE relocation entry. arm-poky-linux-gnueabi-gcc-4.9 default does not enable '-fpic', so there is not .got section and R_ARM_GOT_BREL in built-in.o. And in the final u-boot elf image, all relocation entries are R_ARM_RELATIVE. we can pass '-fno-pic' to xxx-gcc to disable pic. whether the toolchain internally enables or disables pic, '-fno-pic' can work well. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: Disable "DISCARD" for secure section if CONFIG_ARMV7_SECURE_BASE isn't ↵Wang Dongsheng2016-01-31-13/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | defined "DISCARD" will remove ._secure.text relocate, but PSCI framework has already used some absolute address those need to relocate. Use readelf -t -r u-boot show us: .__secure_start addr: 601408e4 .__secure_end addr: 60141460 60141140 00000017 R_ARM_RELATIVE 46 _secure_monitor: 47 #ifdef CONFIG_ARMV7_PSCI 48 ldr r5, =_psci_vectors 60141194 00000017 R_ARM_RELATIVE 6014119c 00000017 R_ARM_RELATIVE 601411a4 00000017 R_ARM_RELATIVE 601411ac 00000017 R_ARM_RELATIVE 64 _psci_table: 66 .word psci_cpu_suspend ... 72 .word psci_migrate 60141344 00000017 R_ARM_RELATIVE 6014145c 00000017 R_ARM_RELATIVE 202 ldr r5, =psci_text_end Solutions: 1. Change absolute address to RelAdr. Based on LDR (immediate, ARM), we only have 4K offset to jump. Now PSCI code size is close to 4K size that is LDR limit jump size, so even if the LDR is based on the current instruction address, there is also have a risk for RelAdr. If we use two jump steps I think we can fix this issue, but looks too hack, so give up this way. 2. Enable "DISCARD" only for CONFIG_ARMV7_SECURE_BASE has defined. If CONFIG_ARMV7_SECURE_BASE is defined in platform, all of secure will in the BASE address that is absolute. Signed-off-by: Wang Dongsheng <dongsheng.wang@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | arm: cache: Implement cache range check for v7Marek Vasut2016-01-31-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to aid tracking down cache alignment issues. In case DEBUG is defined in the cache.c, this code will check alignment of each attempt to flush/invalidate data cache and print a warning if the alignment is incorrect. If DEBUG is not defined, this code is optimized out. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@konsulko.com>
* | | arm: Remove S bit from MMU section entryMarek Vasut2016-01-31-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Restore the old behavior of the MMU section entries configuration, which is without the S-bit. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org>
* | | arm: Replace test for CONFIG_ARMV7 with CONFIG_CPU_V7Marek Vasut2016-01-31-3/+3
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arch/arm/lib/cache-cp15.c checks for CONFIG_ARMV7 and if this macro is set, it configures TTBR0 register. This register must be configured for the cache on ARMv7 to operate correctly. The problem is that noone actually sets the CONFIG_ARMV7 macro and thus the TTBR0 is not configured at all. On SoCFPGA, this produces all sorts of minor issues which are hard to replicate, for example certain USB sticks are not detected or QSPI NOR sometimes fails to write pages completely. The solution is to replace CONFIG_ARMV7 test with CONFIG_CPU_V7 one. This is correct because the code which added the test(s) for CONFIG_ARMV7 was added shortly after CONFIG_ARMV7 was replaced by CONFIG_CPU_V7 and this code was not adjusted correctly to reflect that change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-01-29-1/+22
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| * | ARM: tegra: shut down USB device controller at bootStephen Warren2016-01-28-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When loading U-Boot into RAM over USB protocols using tools such as tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device mode controller is initialized and enumerated by the host PC running the tool. Unfortunately, these tools do not shut down the USB controller before executing the downloaded code, and so the host PC does not "de-enumerate" the USB device. This patch implements optional code to shut down the USB controller when U-Boot boots to avoid leaving a stale USB device present. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-netTom Rini2016-01-28-10/+6
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| * | arm: ls102xa: Rewrite the logic of ft_fixup_enet_phy_connect_type()Bin Meng2016-01-28-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | eth_get_dev_by_index() is an API which is not available in driver model. Use eth_get_dev_by_name() instead, which can also simplifly the code logic a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-01-28-36/+452
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| * | | x86: Correct spi node aliasBin Meng2016-01-28-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With recent changes spi node was moved to a place as a subnode under pch, so update the alias to refer to its correct place as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | x86: config option for loading ACPI table from QEMUMiao Yan2016-01-28-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a config option for loading ACPI table from QEMU. When enabled, U-Boot won't generate ACPI tables, but use those provided by QEMU. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: qemu: add the ability to load and link ACPI tables from QEMUMiao Yan2016-01-28-0/+322
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the ability to load and link ACPI tables provided by QEMU. QEMU tells guests how to load and patch ACPI tables through its fw_cfg interface, by adding a firmware file 'etc/table-loader'. Guests are supposed to parse this file and execute corresponding QEMU commands. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: qemu: setup PM IO base for ACPI in southbridgeMiao Yan2016-01-28-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable ACPI IO space for piix4 (for pc board) and ich9 (for q35 board) Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: qemu: re-structure qemu_fwcfg_list_firmware()Miao Yan2016-01-28-17/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Re-write the logic in qemu_fwcfg_list_firmware(), add a function qemu_fwcfg_read_firmware_list() to handle reading firmware list. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * | | x86: baytrail: Add option to disable the internal UART to setup_early_uart()Stefan Roese2016-01-28-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a parameter to the function setup_early_uart() to either enable or disable the internal BayTrail legacy UART. Since the name setup_early_uart() does not match its functionality any more, lets rename it to setup_internal_uart() as well in this patch. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-07 19:03:57 +0000