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* MLK-11784 imx: mx7: uboot plugin change for mfgtoolYe.Li2015-11-02-0/+19
| | | | | | | | | | Fixed the issue that mfgtool failed to download u-boot with plugin enabled. The u-boot plugin common codes should not call rom___pu_irom_hwcnfg_setup when using serial download mode. rom___pu_irom_hwcnfg_setup will load the IVT2 image from boot media, but this is invalid for USB serial download mode. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11553 imx: mx7 fix typo for showclocksPeng Fan2015-09-15-2/+2
| | | | | | | This piece of code is for mx7, we should not use do_mx6_showclocks. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11528 imx: mx6ul check fuse before init beePeng Fan2015-09-10-1/+11
| | | | | | | | | | | Need to check fuse bit 25 of bank 0 word 4 before initialize bee. The bit: 0 means bee enabled, 1 means bee disabled. If disabled, continuing initialize bee will cause system hang, so need to check this bit before initialize bee. Add macro to enable BEE in header file, default disabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11505 imx: mx6ul: Disable the LCDIF before system resetYe.Li2015-09-08-0/+9
| | | | | | | | | | We meet reset failure on mx6ul 9x9 evk. The internal reset logic between MMDC and functional modules seems relate with the issue. Turn off the LCDIF to stop DDR access before reset to avoid this possible internal reset problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11408-2 imx: mx7d: Isolate 26 IP resources to domain 0 for A coreYe.Li2015-08-25-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | In current design, if any peripheral was assigned to both A7 and M4, it will receive ipg_stop or ipg_wait when any of the 2 platforms enter low power mode. We will have a risk that, if A7 enter wait, M4 enter stop, peripheral will have chance to get ipg_stop and ipg_wait asserted same time. There are 26 peripherals impacted by this IC issue: SIM2(sim2/emvsim2) SIM1(sim1/emvsim1) UART1/UART2/UART3/UART4/UART5/UART6/UART7 SAI1/SAI2/SAI3 WDOG1/WDOG2/WDOG3/WDOG4 GPT1/GPT2/GPT3/GPT4 PWM1/PWM2/PWM3/PWM4 ENET1/ENET2 Software Workaround: The solution is set M4 to a different domain with A core. So the peripherals are not shared by them. This way requires the uboot implemented the RDC driver and set the 26 IPs above to domain 0 only. CM4 image will set the M4 to domain 1 only. This patch enables the CONFIG_MXC_RDC for mx7d SABRESD board and ARM2 boards, and setup the 26 IP resources to domain 0. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11408-1 imx: mx7d: Add mx7d RDC driver supportYe.Li2015-08-25-0/+190
| | | | | | | Add the peripherals/masters definitions and registers base addresses for mx7d RDC. Enable the RDC driver by setting CONFIG_MXC_RDC. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10957: ARM: mx6qp: do not turn off PURobin Gong2015-07-31-1/+2
| | | | | | | | | There is narrow window that PRE driver is ready but GPU driver probe later, and the later GPU driver turn on PU may cause 'PRE hang' issue. To simplify thing, do not turn off PU in u-boot. Signed-off-by: Robin Gong <b38343@freescale.com> (cherry picked from commit 6b0787b726e2ff32210d742d93ecd3f4bb2ae402)
* MLK-10932-2 ARM: imx7: imx-regs: add disconnect_from_pc APIPeter Chen2015-07-14-1/+2
| | | | | | | | | Add disconnect_from_pc API which is used to disconnect the connection with PC which is established at rom code. Tested-by: Spring Zhang <b17931@freescale.com> Tested-by: Zhang Sanshan <b51434@freescale.com> Signed-off-by: Peter Chen <peter.chen@freescale.com>
* MLK-10932-1 ARM: imx6: imx-regs: add disconnect_from_pc APIPeter Chen2015-07-14-1/+2
| | | | | | | Add disconnect_from_pc API which is used to disconnect the connection with PC which is established at rom code. Signed-off-by: Peter Chen <peter.chen@freescale.com>
* MLK-11228-2 android: Add fastboot command "reboot-bootloader" supportYe.Li2015-07-13-0/+12
| | | | | | | | | enable fastboot command: "fastboot reboot-bootloader" After type this command, the board will reboot to bootloader mode. Set ANDROID_FASTBOOT_BOOT flag in SNVS_LPGPR before reboot. Signed-off-by: Zhang Sanshan <b51434@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11228-1 android: Integrate community fastboot with FSL i.MX fastbootYe.Li2015-07-13-79/+10
| | | | | | | | | | | | | | | | | | | | | 1. Replace the UDC driver with community's USB gadget d_dnl driver. 2. Integrate the FSL SD/SATA/NAND flash operations, since the GPT and EFI partitions are not support by i.MX. 3. Add FDT support to community's android image. 4. Change the booti command to boota, due to the booti has been used for ARM64 image boot. 5. Modify boota implementation to load ramdisk and fdt to their loading addresses specified in boot.img header, while bootm won't do it for android image. 6. Modify the android image HAB implementation. Authenticate the boot.img on the "load_addr" for both SD and NAND. 7. Enable new configuration CONFIG_FSL_FASTBOOT for Freescale's fastboot with relevant header file "fsl_fastboot.h". While disabling the configuration, the community fastboot is used. 8. Use community's way to combine cmdline in boot.img and u-boot environment, not overwrite the cmdline in boot.img Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11216-1 imx:mx7d_12x12_ddr3_arm2 add missed Kconfig filesPeng Fan2015-07-03-0/+5
| | | | | | Add missed Kconfig files for mx7d_12x12_ddr3_arm2 board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11201 mx7: clock: Fix PLL divider for the 100MHz caseFabio Estevam2015-06-29-1/+1
| | | | | | | We should divide the 1000MHz ENET PLL clock by 10 in order to achieve 100MHz, so fix the divider accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MLK-11159-2 Revert "MLK-11028 imx: mx6qp change L2 prefetch offset to 0"Robby Cai2015-06-24-1/+1
| | | | | | | | | | | | This reverts commit 2bc93d766dee5d5dc33035446f82622c4f1fb784. After further investigation, find L2 prefetch offset setting of 0xF is not the root cause for USB stress reboot failure. With the fix in USB driver, and L2 prefetch offset setting of 0xF, the reboot stress test has passed 4-days both on imx6q and imx6qp sabreauto board. Signed-off-by: Robby Cai <r63905@freescale.com> (cherry picked from commit 6e9282c2567b2820699fa55d2c6bf0ab78e992d6)
* MLK-11135-2 imx: mx6ul: Add MX6UL LPDDR2 ARM2 board supportYe.Li2015-06-19-0/+5
| | | | | | | | | Add MX6UL LPDDR2 ARM2 board BSP codes, supported peripherals: SD1, eMMC(USDHC2), USB OTG1, I2C, ENET2, PMIC. Due to a board issue, the SD1 only supports 1 bit bus width. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11101 imx: mx6: Move the set_wdog_reset out of CONFIG_LDO_BYPASS_CHECKYe.Li2015-06-12-22/+22
| | | | | | | | Since the 6ul does not enable the CONFIG_LDO_BYPASS_CHECK, but have to use the set_wdog_reset function. Need to move the funciton out of CONFIG_LDO_BYPASS_CHECK to resolve build issue. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11028 imx: mx6qp change L2 prefetch offset to 0Peng Fan2015-06-12-1/+1
| | | | | | Change L2 prefetch offset to 0 to make system stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-11064 imx: mx6qp: Adjust AQos settings for peripheralsYe.Li2015-06-08-0/+3
| | | | | | | | | To resolve USB camera bandwidth issue, the patch sets recommended AQoS setting from IC team value for peripheral and only on imx6qp. The address is: 0xbb0608, the value is: 0x80000201 Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-11050 ARM: imx6: configure the PMIC_STBY_REQ pin as open drainBai Ping2015-06-05-0/+9
| | | | | | | Configure the PMIC_STBY_REQ pin as open drain 100K according to the design team's requirement for the PMIC_STBY_REQ pin. Signed-off-by: Bai Ping <b51503@freescale.com>
* MLK-11008 imx: HAB: Fix secure boot configuration and build issueYe.Li2015-06-01-1/+1
| | | | | | | | | | | 1. There is conflict when building secure boot, because some common codes for MPC are included by using same configuration. So modify the makefile to get rid of them. 2. The 6UL arch config is missed in hab.h. Fix this issue by using the CONFIG_ROM_UNIFIED_SECTIONS. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10981 mxc: ocotp fix hole in shadow registersPeng Fan2015-05-29-1/+2
| | | | | | | | | | | | | | | | | | | | There is a hole in shadow registers address map of size 0x100 between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, we should account for this hole in address space. Similar hole exists between bank 14 and bank 15 of size 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. Note: iMX6SL has only 0-7 banks and there is no hole. Note: iMX6UL doesn't have this one. When reading, we use register offset, so need to account for holes to get the correct address. When writing, we use bank/word index, there is no need to account for holes, always use bank/word index from fuse map. Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10972-1 imx: mx7d Add SION bit for i2c pin muxPeng Fan2015-05-26-28/+28
| | | | | | Add SION bit for all i2c pin mux settings. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10958 imx: mx6ul support Bus Encryption EnginePeng Fan2015-05-25-1/+507
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to support Bus Encryption Engine(BEE) for i.MX 6UL. Supported feature: 1. SNVS key and soft key 2. CTR and ECB mode 3. Specify address region to bee. Two commands are included: bee init [key] [mode] [start] [end] - BEE block initial "Example: bee init 1 1 0x80000000 0x80010000\n" bee test [region] "Example: bee test 1\n" Mapping: [0x10000000 - (0x10000000 + size - 1)] : [start - (start + size - 1)] [0x30000000 - (0x30000000 + IRAM_SIZE - 1)] : [IRAM_BASE_ADDR - (IRAM_BASE_ADDR + IRAM_SIZE - 1)] Whatever start is, start - (start + size -1) will be fixed mapping to 0x10000000 - (0x10000000 + size - 1) Since default AES region's protected size is SZ_512M, so on mx6ul evk board, you can not simply run 'bee init', it will overlap with uboot execution environment, you can use 'bee init 0 0 0x80000000 0x81000000'. If want to use bee, Need to define CONFIG_CMD_BEE in board configuration header file, since CONFIG_CMD_BEE default is not enabled. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10956 imx: mx6ul: Change BSP name and dtb name for 14x14 packageYe.Li2015-05-25-6/+6
| | | | | | | | | | | | | | Since there is another 9x9 package for mx6ul, modify the BSP names of ddr3 arm2 board and evk board to add 14x14 package info. Also modify the loaded dtb file to align with kernel. After the change, the build target for mx6ul ddr3 arm2 board is: mx6ul_14x14_ddr3_arm2_config and the build target for mx6ul evk board is: mx6ul_14x14_evk_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10546-2 imx: mx7 implement reset_miscPeng Fan2015-05-22-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | On mx7d 12x12 lpddr3 arm2 board, POR_B reset in uboot will fail stress reset test, and hangs in rom code. Rom log buffer show thats wrong hab_image_entry and runs into serial download mode. Also there is no time delay reset circuit for this board. We found when disable CONFIG_VIDEO, all seems fine. Actually, only the following piece of code can make stress reset ok, " writel(LCDIF_CTRL1_VSYNC_EDGE_IRQ, &regs->hw_lcdif_ctrl1_clr); while (--timeout) { if (readl(&regs->hw_lcdif_ctrl1) & LCDIF_CTRL1_VSYNC_EDGE_IRQ) break; udelay(1); } " Here we use lcdif_power_down API which is better to shutdown lcdif same as the way used in arch_preboot_os. Implement reset_misc for mx7, since it does not hurt for others boards. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10936 imx: mx7d: Change to use bootrom_sw_info for getting boot deviceimx_3.14.38_6ul_engrYe.Li2015-05-20-20/+31
| | | | | | | | | | | | | | | | | | | | | On MX7D, boot rom can provide some boot information such as boot device, arm freq, axi freq, etc. (see the structure below) Offset Byte4 | Byte3 | Byte2 | Byte1 0x0 Reserved | Boot Device Type | Boot Device Instance | Reserved 0x4 ARM core frequency(in Hz) 0x8 AXI bus frequency(in Hz) 0x0C DDR frequency(in Hz) 0x10 GPT1 input clock frequency(in Hz) 0x14 Reserved 0x18 0x1C The boot information can be accessed by get the pointer at 0x1E8. This patch changes the u-boot to use the new approach. When manufacture boot, the info recorded is the actual SD port, not the failed device. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10839: arm: imx: mx7d 19x19 lpddr3 arm2 board supportAdrian Alonso2015-05-13-0/+5
| | | | | | | | | | | | | * Add mx7d_19x19_lpddr3_arm2 target board supprt * Enable i2c, spinor, usb, usdhc, qspi, enet, uart * Build targets mx7d_19x19_lpddr3_arm2_defconfig mx7d_19x19_lpddr3_arm2_eimnor_defconfig - Set EIMNOR settings for Intel Sibley Asynchronous mode - Set flash sector size for 256kb (erase block size) Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10884 imx: MX6SX: Fix IOMUXC GPR registers access issueYe.Li2015-05-13-2/+2
| | | | | | | | The iomuxc structure has changed to add 0x4000 offset for i.MX6SX and UL, so when using this structure to access gpr registers needs to change the base address to IOMUXC_BASE_ADDR. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10870 imx: mx7d: Implement to get board serial numberYe.Li2015-05-11-1/+7
| | | | | | Get the Unique ID of the chip from the fuse TESTER0 and TESTER1. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10829-1 imx:mx6sx correct i2c and video clock settingsPeng Fan2015-05-06-13/+3
| | | | | | | | Change MXC_CCM_CCGR6_I2C4_xx to MXC_CCM_CCGR6_I2C4_SERIAL_xx Remove duplicated mxs_set_vadcclk Correct enable_pll_video usage Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10817 imx:mx6ul_ddr3_arm2 add mx6ul ddr3 arm2 board supportPeng Fan2015-05-05-0/+5
| | | | | | | | | | | | | Add board code for mx6ul ddr3 arm2 board. QSPI, USDHC, ENET, USB, VIDEO, SPINOR, EIMNOR Add sd1, qspi and spinor boot support DDR script is 1.02 version. Signed-off-by: Fugang Duan <b38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10821 imx: mx6ulevk: Add board support for mx6ulevkYe.Li2015-05-05-0/+5
| | | | | | | | | | | Add BSP codes to support modules on the board: I2C, SD/eMMC, NAND, QSPI, FEC1/FEC2, USB, LCDIF, 74LV, Serial DDR version: 1.0 Build target: mx6ulevk_config mx6ulevk_qspi1_config Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10812-3 imx:mx6ul PAD_CTL_SPEED_LOW for mx6ulPeng Fan2015-05-05-1/+1
| | | | | | PAD_CTL_SPEED_LOW for mx6ul same with mx6sx. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10812-2 imx:mx6ul add clock supportPeng Fan2015-05-05-61/+421
| | | | | | | | | | | | add i.MX6UL clock related settings/macros/apis When using TFT43AB, its pixel size is 480x272 which needs a slow pix clock. Without apply the test_div in PLL video, we can't get the pix clock in the rate. So change the LCDIF clock calculation to use the test_div. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10812-1 imx:mx6 add i2c4 supportPeng Fan2015-05-05-6/+23
| | | | | | I2C4 support for i.MX Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10808-5 imx: mx6ul: Update soc relevant settingsYe.Li2015-05-05-9/+25
| | | | | | | Remove PCIe, xPU power, PL310 L2 Cache for MX6UL. Update FEC MAC address, WDOG settings, USDHC clock rate. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-4 imx: Move system counter driver to imx-commonYe.Li2015-05-04-9/+18
| | | | | | | | | | | | | Since the system counter driver will also be used by mx6ul, move this timer driver to imx-common and rename it as syscounter.c For mx6ul and mx7, configurations are used for choose the GPT timer or system counter timer (default). GPT timer: CONFIG_GPT_TIMER System counter timer: CONFIG_SYSCOUNTER_TIMER Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-3 imx: mx6ul: Update imx registers head fileYe.Li2015-05-04-33/+114
| | | | | | Update imx registers base address for i.MX6UL Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-2 imx: mx6ul: Add pins IOMUX head fileYe.Li2015-05-04-0/+1068
| | | | | | | Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10808-1 imx: mx6ul: Add i.MX6UL CPU typeYe.Li2015-05-04-2/+5
| | | | | | | | | Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime. The 0x64 is defined as i.MX6Ul CPU type value in RM, but the value has been occupied by i.MX6D as a dummy CPU type. So we also need change i.MX6D to a invalid value 0x67. Signed-off-by: Ye.Li <B37916@freescale.com>
* MLK-10774-52 nand: mxs correct MXS_DMA_ALIGNMENTPeng Fan2015-04-29-1/+1
| | | | | | | | | | | | We should align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN, otherwise we may encounter errors, " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10708 imx:mx6qp Update Saturation THR for PRExPeng Fan2015-04-29-4/+4
| | | | | | | | Update settings for PRE. Value for Saturation THR of PREx, changed from 0x20 to 0x10 to make system more stable. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 02e7090604e55d9690532294b02b499609d46e63)
* MLK-10702 imx: mx7d: clock: correct fec MDC root clockFugang Duan2015-04-29-1/+1
| | | | | | | | In i.MX7d platform, fec MDC root clock is ENET_AXI_ROOT_CLK, not ipg clock, correct it. Signed-off-by: Fugang Duan <B38611@freescale.com> (cherry picked from commit 07105e18dd0899c47ef80d3fddecf3ef250d895a)
* MLK-10774-48 imx: mx7 update hab_caam_clock_enablePeng Fan2015-04-29-11/+8
| | | | | | | Merge hab_caam_clock_enable and hab_caam_clock_disable into one function Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* ENGR00329484-2 ARM:MX6: Clear Align bit in SCTLRPeng Fan2015-04-29-0/+3
| | | | | | | | | | | This problem is found when debugging QuadSPI. When "A" bit is enabled, unaligned access will cause data abort exception. Actually, we do not want this exception. So clear the align bit for MX6 SOCs. Tested this code with android team colleague and did not find problem. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit aa76a7e472e34bc59554f9932d611b1047d24590)
* MLK-10674-2 imx: mx6qp settings for PREPeng Fan2015-04-29-0/+38
| | | | | | | | | | | | | | | | | | | | | | Since the following piece settings can not be in DCD table, we add them in enable_ipu_clock. " setmem /32 0x00bb048c = 0x00000002 ## Bypass IPU1 QoS generator setmem /32 0x00bb050c = 0x00000002 ## Bypass IPU2 QoS generator setmem /32 0x00bb0690 = 0x00000200 ## Bandwidth THR for of PRE0 setmem /32 0x00bb0710 = 0x00000200 ## Bandwidth THR for of PRE1 setmem /32 0x00bb0790 = 0x00000200 ## Bandwidth THR for of PRE2 setmem /32 0x00bb0810 = 0x00000200 ## Bandwidth THR for of PRE3 setmem /32 0x00bb0694 = 0x00000020 ## Saturation THR for of PRE0 setmem /32 0x00bb0714 = 0x00000020 ## Saturation THR for of PRE1 setmem /32 0x00bb0794 = 0x00000020 ## Saturation THR for of PRE2 setmem /32 0x00bb0814 = 0x00000020 ## Saturation THR for of PRE " CONFIG_VIDEO_IPUV3 is always defined in mx6sabre_common.h, the settings sure will effect. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> (cherry picked from commit 61cec88a59ebf450dd1352d81e03b5aa842e1d71)
* MLK-10647 armv7: Fix Dcache disable issue on i.MX7Ye.Li2015-04-29-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The issue on the i.MX7D is that, there is one cache-able memory access between the L1 and L2 cache flush by calling the flush_dache_all-> v7_maint_dcache_all() [Flush L1 and L2 cache) which written in the C code. L1-cache-flush -> This will flush L1 cache to L2 cache in the end. Cache-able memory access -> This will have the chance cause the L1 line-fill with dirty data from L2 cache(L1 cache-line dirty, L2 clean) L2-cache-flush -> This will only flush L2 cache to L3, but still some dirty data on the L1 cacheline. After C & M bit clean, -> The dirty data on the L1 cache line lost, which will cause memory coherent issue if that dirty cache line has some useful data The only problem here is: there is one cache-cable memory access between L1 and L2 cache flush. This patch should works fine on the i.MX6 and i.MX7. The second cache flush have zero impact on the i.MX6, but this is really need for the i.MX7D platform due to the L1 line-fill during the first dcache_flush. And the second flush will not bring in the L1 dirty cache line due to the C bit is clear now, which means the dcache is disabled. Acked-by: Jason Liu<r64343@freescale.com> Reviewed-by: Jason Liu<r64343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> (cherry picked from commit f5d5f07fba936c4bb05c887de9d72fb75b3dc0f2) (cherry picked from commit 86c784cf4c4b633d37a76de7d47155c08f75dc82)
* MLK-10774-46 imx:mx6sx use correct GPR addressPeng Fan2015-04-29-1/+1
| | | | | | Use correct GPR address. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-45 imx:mx6sx add SION for i2c pin muxPeng Fan2015-04-29-20/+20
| | | | | | | | Add SION for i2c pin mux, otherwise will cause error. Found this problem on mx6sxsabreauto board. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* MLK-10774-44 imx:mx6 fix is_soc_revPeng Fan2015-04-29-1/+1
| | | | | | | is_soc_rev should be casted to signed int, otherwise may incur errors when detecting cpu types. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
generated by cgit v1.1 at 2024-12-25 06:21:01 +0000