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| * | | | armv8/ls1043aqds: Add lpuart supportWenbin Song2016-01-27-0/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add lpuart support using the driver model. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | armv8/ls1043aqds: Spilt off board device treeWenbin Song2016-01-27-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move new /chosen node out of the board device tree. Signed-off-by: Wenbin Song <wenbin.song@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | secure_boot: enable chain of trust for PowerPC platformsAneesh Bansal2016-01-27-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chain of Trust is enabled for PowerPC platforms for Secure Boot. CONFIG_BOARD_LATE_INIT is defined. In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | secure_boot: enable chain of trust for ARM platformsAneesh Bansal2016-01-27-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Chain of Trust is enabled for ARM platforms (LS1021 and LS1043). In board_late_init(), fsl_setenv_chain_of_trust() is called which will perform the following: - If boot mode is non-secure, return (No Change) - If boot mode is secure, set the following environmet variables: bootdelay = 0 (To disable Boot Prompt) bootcmd = CONFIG_CHAIN_BOOT_CMD (Validate and execute Boot script) Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | secure_boot: create function to determine boot modeAneesh Bansal2016-01-27-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A function is created to detrmine if the boot mode is secure or non-secure for differnt SoC's. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | secure_boot: split the secure boot functionality in two partsAneesh Bansal2016-01-27-23/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are two phases in Secure Boot 1. ISBC: In BootROM, validate the BootLoader (U-Boot). 2. ESBC: In U-Boot, continuing the Chain of Trust by validating and booting LINUX. For ESBC phase, there is no difference in SoC's based on ARM or PowerPC cores. But the exit conditions after ISBC phase i.e. entry conditions for U-Boot are different for ARM and PowerPC. PowerPC: If Secure Boot is executed, a separate U-Boot target is required which must be compiled with a diffrent Text Base as compared to Non-Secure Boot. There are some LAW and TLB settings which are required specifically for Secure Boot scenario. ARM: ARM based SoC's have a fixed memory map and exit conditions from BootROM are same irrespective of boot mode (Secure or Non-Secure). Thus the current Secure Boot functionlity has been split into two parts: CONFIG_CHAIN_OF_TRUST This will have the following functionality as part of U-Boot: 1. Enable commands like esbc_validate, esbc_halt 2. Change the environment settings based on bootmode, determined at run time: - If bootmode is non-secure, no change - If bootmode is secure, set the following: - bootdelay = 0 (Don't give boot prompt) - bootcmd = Validate and execute the bootscript. CONFIG_SECURE_BOOT This is defined only for creating a different compile time target for secure boot. Traditionally, both these functionalities were defined under CONFIG_SECURE_BOOT. This patch is aimed at removing the requirement for a separate Secure Boot target for ARM based SoC's. CONFIG_CHAIN_OF_TRUST will be defined and boot mode will be determine at run time. Another Security Requirement for running CHAIN_OF_TRUST is that U-Boot environemnt must not be picked from flash/external memory. This cannot be done based on bootmode at run time in current U-Boot architecture. Once this dependency is resolved, no separate SECURE_BOOT target will be required for ARM based SoC's. Currently, the only code under CONFIG_SECURE_BOOT for ARM SoC's is defining CONFIG_ENV_IS_NOWHERE Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | secure_boot: include/configs: move definition of CONFIG_CMD_BLOBAneesh Bansal2016-01-27-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_CMD_BLOB must be defined in case of Secure Boot. It was earlier defined in all config files. The definition has been moved to a common file which is included by all configs. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | secure_boot: include/configs: make secure boot header file uniformAneesh Bansal2016-01-27-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The file fsl_secure_boot.h must be included in config file for Secure Boot. This is not required to be protected by any macro. CONFIG_FSL_CAAM must be defined and CONFIG_CMD_HASH should be turned on. The above was missing in some config files and all files have been made uniform in this respect. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Acked-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | armv8: ls2040a: Add support of LS2040A SoCPratiyush Mohan Srivastava2016-01-25-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's LS2040A is a another personality of LS2080A SoC without AIOP support consisting of 4 armv8 cores. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | armv8: Enable all 8 DPMAC ports in LS2080A PersonalityPratiyush Mohan Srivastava2016-01-25-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2080A has support for 8 DPMAC ports out of which only 5 ports can be used at a time. Enabling all 8 DPMAC ports of LS2080A personality. Signed-off-by: Pratiyush Mohan Srivastava <pratiyush.srivastava@freescale.com> Acked-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | armv8: fsl-layerscape: fixes lsch2 serdes registers defineShaohui Xie2016-01-25-20/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes lsch2 SerDes registers define according to LS1043A RM Rev D. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | arm: ls1021a: Adjust sata register default valuesTang Yuantian2016-01-25-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updated the default sata register values to enhance the performance and stability. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | driver/ddr/fsl: Add workaround for A009663Shengzhou Liu2016-01-25-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A-009663 workaround requires to set DDR_INTERVAL[BSTOPRE] to 0 before setting DDR_SDRAM_CFG[MEM_EN] and set DDR_INTERVAL[BSTOPRE] to the desired value after DDR initialization has completed. When DDR controller is configured to operate in auto-precharge mode(DDR_INTERVAL[BSTOPRE]=0), this workaround is not needed. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | armv8: fsl-lsch3: fixup SYSCLK frequency in device treePrabhakar Kushwaha2016-01-25-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SYSCLK frequency is dependent on on-board switch settings. It may vary as per requirement. boot-loader is aware of board switch configurations. So Fixup Linux device tree from boot-loader. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> CC: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | | | fsl/ddr: Add workaround for ERRATUM_A009942Shengzhou Liu2016-01-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the receive data training, the DDRC may complete on a non-optimal setting that could lead to data corruption or initialization failure. Workaround: before setting MEM_EN, set DEBUG_29 register with specific value for different data rates. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | | | Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-01-27-91/+160
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| * | | | ppc: xilinx-ppc4xx: Port to DM serialRicardo Ribalda Delgado2016-01-27-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xilinx_uartlite has been ported to DM, this patch makes the xilinx-ppc405-generic and the xilinx-ppc440-generic boards use the new DM driver. Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM64: zynqmp: Add support for SD1 boot modeMichal Simek2016-01-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SD1 boot mode is using different bootmode values. Add support for this mode used on DC1. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM64: zynqmp: Modify the SD and QSPI bootmode valuesSiva Durga Prasad Paladugu2016-01-27-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify the SD bootmode value to 0x3 as per latest spec. Also add new boot mode QSPI 32 bit boot mode Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM64: zynqmp: DT: Fix UART compatible stringSoren Brinkmann2016-01-27-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ZynqMP has r1p12 not r1p8. r1p12 contains break detection support. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM64: zynqmp: Correct the watchdog timer interrupt numberPunnaiah Choudary Kalluri2016-01-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Corrected the watchdog timer interrupt number. Origin value was for CSUPMU watchdog. Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM64: zynqmp: Fix coding style in phy nodeMichal Simek2016-01-27-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trivial fix. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM64: zynqmp: Add initial support for the first siliconMichal Simek2016-01-27-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add basic configuration for the first silicon. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM64: zynqmp: Use the same U-Boot version with/without ATFMichal Simek2016-01-27-8/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove SECURE_IOU option which is not needed. U-Boot itself can detect which EL level it is on and based on that use do platform setup. It also simplify usage because one Kconfig entry is gone. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: Move spi node to aligned locationMichal Simek2016-01-27-27/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keep nodes aligned. Signed-off-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: Fix all remaining zynq platform to use stdout-pathMichal Simek2016-01-27-12/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix console setup for all remaining zynq boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: Clean DTSI coding styleMichal Simek2016-01-27-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix minor indentation problems. Signed-off-by: Michal Simek <monstr@monstr.eu> Reviewed-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Reviewed-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: Do not select options if SPL is not enabledMichal Simek2016-01-27-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Zynq setups some default options for SPL but not all targets are enabling SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ARM: zynq: Remove memory division by 2 for ECC caseMichal Simek2016-01-27-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For ECC case u-boot divided memory by 2 because one u-boot could be used for both cases when ECC is off or on. Remove this division and make sure that dts file contain the correct memory size when ECC is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | microblaze: Remove empty file - cpu.cMichal Simek2016-01-27-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to have empty unused file in architecture code. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | microblaze: Wire-up debug_uart in asmMichal Simek2016-01-27-0/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | | serial: uartlite: Move driver to DMMichal Simek2016-01-27-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPL DM too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Thomas Chou <thomas@wytron.com.tw>
| * | | | ppc: dts: Add device tree for xilix-ppc4xx-genericRicardo Ribalda Delgado2016-01-27-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device tree example file for xilinx-ppc440-generic and xilinx-ppc405-generic Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
| * | | | mailaddr: Update mail addressRicardo Ribalda Delgado2016-01-27-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The old mail address will stop working soon. Update it all the files Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
| * | | | xilinx-ppc440: Remove support for v5fx30tevalRicardo Ribalda Delgado2016-01-27-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is just a specialized version of xilinx-ppc440 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ppc: xilinx-ppc405: Remove support for fx12mmRicardo Ribalda Delgado2016-01-27-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is just a specialized version of the xilinx-ppc405 Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
| * | | | ppc: xilinx-ppc440: Remove support for ml507Ricardo Ribalda Delgado2016-01-27-4/+0
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ml507 is just a specialized version of the xilinx-ppc440-generic Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Michal Simek <michal.simek@xilinx.com>
* | | | arm: mvebu: Add support for the Armada XP theadorable boardStefan Roese2016-01-27-1/+151
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the Armada XP (MV78260) based theadorable board. Its equipped with onboard DDR3, UART, ethernet, I2C, SPI NOR, LCD and SATA (SSD) interfaces / devices. Two defconfigs are added: theadorable_defconfig: The production U-Boot version with a stripped down drivers and feature list. This removes networking, USB and PCI support. theadorable_debug_defconfig: The debugging / testing U-Boot version with full support for all drivers. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-01-26-19/+186
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| * | | sunxi: Add suport for A83T based Banana-pi M3 BoardVishnu Patekar2016-01-26-1/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dts and defconfig for Banana-pi M3 board. It has 2G LPDDR3, UART, ethernet, USB, HDMI, USB Sata, MIPI DSI, mic, AP6212 Wifi, etc on it. It is paired with AXP813 PMIC which is almost same as AXP818. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> [hdegoede@redhat.com: rename to Sinovoip_BPI_M3_defconfig/sun8i-a83t-sinovoip-bpi-m3.dts] Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: Add support for LPDDR3 for A83TVishnu Patekar2016-01-26-5/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Banana-pi M3 has LPDDR3 DRAM. this adds support for LPDDR3 for A83T. Mostly the timing parameters are different from DDR3. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: Groundwork to support new dram type for A83TVishnu Patekar2016-01-26-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Different A83T boards have different DRAM types. Banapi M3 has LPDDR3, Allwinner Homlet v1.2 has DDR3. This adds groundwork to support for new DRAM type for A83T. Introduce CONFIG_DRAM_TYPE, It'll be 3 for DDR3 and 7 for LPDDR3, must be set in respective board defconfig. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: Redundant code cleanup from a83t dram initVishnu Patekar2016-01-26-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This removes the redundant lines of code from mctl_sys_init. Signed-off-by: Vishnu Patekar <vishnupatekar0510@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: Support PSCI ops on Allwinner H3Chen-Yu Tsai2016-01-26-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H3 has the same power sequencing procedure as the A31/A31s, which includes the power clamps. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: Support H3 CCU security switchesChen-Yu Tsai2016-01-26-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | H3's CCU includes some switches which disable non-secure access to some of the more critical clock controls, such as MBUS, PLLs, and main platform busses. Configure them to enable non-secure access. For now the only SoC that has this feature is the H3. For other platforms just use a default (weak) empty function so things do not break. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | sunxi: Support Secure Memory Touch Arbiter (SMTA) in sun8i H3Chen-Yu Tsai2016-01-26-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secure Memory Touch Arbiter is the same thing as the TrustZone Protection Controller found on A31/A31s. Access to many peripherals on the H3 can be controlled by the SMTA, and the settings default to secure access only. This patch supports the new settings, and sets them to allow non-secure access. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-01-26-0/+14
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| * | | | video: Add support for Armada XP LCD controllerStefan Roese2016-01-23-0/+14
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the LCD controller of the Marvell Armada XP SoC. An AXP based custom board port will be added later, to use this driver to display a splash screen via the bmp command later. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> [agust: rebased] Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | | | mips: asm/io.h: Add in <linux/bug.h>Tom Rini2016-01-25-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | As part of the bug.h / BUILD_BUG_* clean up, this file was missed. Signed-off-by: Tom Rini <trini@konsulko.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-01-25-4/+15
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