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* ARM: PSCI: use only r0 and r3 in psci_get_cpu_stack_top()Chen-Yu Tsai2016-06-20-9/+9
| | | | | | | | | | | For psci_get_cpu_stack_top() to be usable in C code, it must adhere to the ARM calling conventions. Since it could be called when the stack is still unavailable, and the entry code to linux also expects r1 and r2 to remain unchanged, stick to r0 and r3. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* sunxi: Add defconfig and dts file for inet86dz boardHans de Goede2016-06-20-0/+294
| | | | | | | | | | | | | | | The inet86dz board is a board used in 7" tablets from various oems. These tablets are a23 based 7" tablets featuring a 1024x600 LCD, 512MB RAM, 4G NAND, rtl8188etv usb wifi, gsl1680 touchschreen, micro-sd slot, 3.5mm headphone jack and a micro-usb otg connector which doubles as charging port. The dts file this commit adds is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Add defconfig and dts file for Polaroid MID2407PXE03 tabletHans de Goede2016-06-20-0/+303
| | | | | | | | | | | | The Polaroid MID2407PXE03 is an a23 based 7" tablet based on a M86_MB V2.0 PCB, featuring a 800x480 LCD, 512MB RAM, 4G NAND, esp8089 wifi, gsl1680 touchschreen, micro-sd slot, 3.5mm headphone jack and a micro-usb otg connector which doubles as charging port. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* sunxi: Select USE_TINY_PRINTFHans de Goede2016-06-20-0/+1
| | | | | | | | This gives us a bit more breathing room wrt our SPL size. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-dmTom Rini2016-06-20-61/+261
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| * clk: convert API to match reset/mailbox styleStephen Warren2016-06-19-55/+204
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following changes are made to the clock API: * The concept of "clocks" and "peripheral clocks" are unified; each clock provider now implements a single set of clocks. This provides a simpler conceptual interface to clients, and better aligns with device tree clock bindings. * Clocks are now identified with a single "struct clk", rather than requiring clients to store the clock provider device and clock identity values separately. For simple clock consumers, this isolates clients from internal details of the clock API. * clk.h is split so it only contains the client/consumer API, whereas clk-uclass.h contains the provider API. This aligns with the recently added reset and mailbox APIs. * clk_ops .of_xlate(), .request(), and .free() are added so providers can customize these operations if needed. This also aligns with the recently added reset and mailbox APIs. * clk_disable() is added. * All users of the current clock APIs are updated. * Sandbox clock tests are updated to exercise clock lookup via DT, and clock enable/disable. * rkclk_get_clk() is removed and replaced with standard APIs. Buildman shows no clock-related errors for any board for which buildman can download a toolchain. test/py passes for sandbox (which invokes the dm clk test amongst others). Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * reset: implement a reset testStephen Warren2016-06-19-0/+32
| | | | | | | | | | | | | | | | | | This adds a sandbox reset implementation (provider), a test client device, instantiates them both from Sandbox's DT, and adds a DM test that excercises everything. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
| * mailbox: add Tegra186 HSP driverStephen Warren2016-06-19-0/+15
| | | | | | | | | | | | | | | | | | | | Tegra186's HSP module implements doorbells, mailboxes, semaphores, and shared interrupts. This patch provides a driver for HSP, and hooks it into the mailbox API. Currently, only doorbells are supported. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
| * sandbox: gpio: doc: Fix parameter documentationmario.six@gdsys.cc2016-06-19-6/+10
| | | | | | | | | | | | | | | | | | | | The documentation of parameters in arch/sandbox/include/asm/gpio.h is either missing or faulty. This patch corrects the documentation. Signed-off-by: Mario Six <mario.six@gdsys.cc> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: uniphier: reserve memory for DRAM PHY training on PH1-LD20Masahiro Yamada2016-06-20-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DRAM PHY layer on PH1-LD20 is able to calibrate PHY parameters periodically. This compensates for the voltage and temperature deviation and improves the PHY parameter adjustment. Instead, it requires 64 byte scratch memory in each DRAM channel for the dynamic training. The memory regions must be reserved in DT before jumping to the kernel. The scratch area can be anywhere in each DRAM channel, but the DRAM init code in SPL currently assigns it at the end of each channel. So, it makes sense to reserve the regions on run-time by U-Boot instead of statically embedding it in the DT in Linux. Anyway, a boot-loader should know much more about memory initialization than the kernel. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: move CONFIG_ARMV8_MULTIENTRY to KconfigMasahiro Yamada2016-06-20-0/+1
| | | | | | | | | | | | I just did not notice this option had an entry in Kconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: uniphier: introduce CONFIG_ARM_UNIPHIER_{32, 64}BITMasahiro Yamada2016-06-20-8/+15
|/ | | | | | | This will make it easier to select config options specific to particular ARM processor generation. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-06-18-4/+117
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| * ARM: socfpga: Sort Kconfig entriesMarek Vasut2016-06-08-4/+4
| | | | | | | | | | | | | | | | Just sort the board entries, no functional change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * ARM: socfpga: add support for IS1 boardPavel Machek2016-06-08-0/+113
| | | | | | | | | | | | | | | | This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbTom Rini2016-06-18-10/+15
|\ \ | | | | | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
| * | usb: xhci: fsl: Add workaround for USB erratum A008751Sriram Dash2016-06-13-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is doing the following: 1. Implementing the errata for LS2080. 2. Adding fixup for fdt for LS2080. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * | armv8/ls2080: Remove workaround for erratum A008751Sriram Dash2016-06-13-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This errata a008751 is applied on Soc specific file currently.This will be moved to a file where all the errata implementation will take place for usb for fsl. This patch removes the errata workaround from soc specific file for LS2080. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
| * | arm64: fsl-layerscape: add get_svr and IS_SVR_REV helperSriram Dash2016-06-13-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms, similar to PPC and ARMv7. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
* | | arm: Fix setjmpAlexander Graf2016-06-17-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The setjmp/longjmp implementation did not work on thumb1 implementations because it used instruction encodings that don't exist on thumb1 yet. This patch limits itself to thumb1 instruction set for 32bit arm and removes a superfluous printf along the way. Signed-off-by: Alexander Graf <agraf@suse.de>
* | | arm, am335x: siemens: enable DM/DTS supportHeiko Schocher2016-06-17-2/+1554
| | | | | | | | | | | | | | | | | | enable basic DM/DTS support for the siemens am335x based boards. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | ARM: dts: AM572x-IDK Initial SupportSchuyler Patton2016-06-13-1/+393
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial DTS support for AM572-IDK evm. Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Schuyler Patton <spatton@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | board: am57xx: Rename TARGET_BEAGLE_X15 as TARGET_AM57XX_EVMLokesh Vutla2016-06-13-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | board/am57xx supports all boards based on am57xx. Rename the taget as TARGET_AM57XX_EVM. Fixes: 74cc8b097d9af ("board: ti: beagle_x15: Rename to indicate support for TI am57xx evms") Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | | armv8: s32v234: Introduce basic support for s32v234evbEddy Petrișor2016-06-13-0/+1787
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for NXP's S32V234 SoC and S32V234EVB board. The S32V230 family is designed to support computation-intensive applications for image processing. The S32V234, as part of the S32V230 family, is a high-performance automotive processor designed to support safe computation-intensive applications in the area of vision and sensor fusion. Code originally writen by: Original-signed-off-by: Stoica Cosmin-Stefan <cosminstefan.stoica@freescale.com> Original-signed-off-by: Mihaela Martinas <Mihaela.Martinas@freescale.com> Original-signed-off-by: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Eddy Petrișor <eddy.petrisor@nxp.com>
* | | board: arm:: Add support for Broadcom BCM23550Steve Rae2016-06-13-0/+1963
| | | | | | | | | | | | | | | | | | Add support for the Broadcom BCM23550 board. Signed-off-by: Steve Rae <srae@broadcom.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-arcTom Rini2016-06-13-21/+84
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| * | | arc: Update data accessors with use of memory barriersAlexey Brodkin2016-06-13-16/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Memory barriers are proven to be a requirement for both compiler and real hardware to properly serialize access to critical data. For example if CPU or data bus it uses may do reordering of data accesses absence of memory barriers might easily lead to very subtle and hard to debug data corruptions. This implementation was heavily borrowed from up to date Linux kernel. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc/cache: Flush & invalidate all caches right before enabling IOCAlexey Brodkin2016-06-13-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to ARC HS databook it is required to flush and disable caches prior programming IOC registers. Otherwise ongoing coherent memory operations may not observe the coherency protocols as expected. But since in ARC HS v2.1 there's no way to disable SLC (AKA L2 cache) we're doing our best flushing and invalidating it. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
| * | | arc/cache: really do invalidate_dcache_all() even if IOC existsAlexey Brodkin2016-06-13-5/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | invalidate_dcache_all() could be used in different use-cases and what is especially important most of those cases won't be related to DMAed data to or from peripherals, i.e. we'll be doing invalidation of data used purely by CPU cores. Given that IOC engine only snoops data that goes through DMA we need to care ourselves about data used only by CPU cores and so remove dependency on IOC from invalidate_dcache_all() and always do real invalidation. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2016-06-13-31/+1674
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| * | | ARM: at91: Fix PMC bit definitionsMarek Vasut2016-06-12-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing parenthesis around the variable into the macro. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | ARM: at91: sama5: Extend boot device autodetectionMarek Vasut2016-06-12-21/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the boot device autodetection from SAMA5D2 only to the entire SAMA5Dx family of microcontrollers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Andreas Bießmann <andreas.devel@googlemail.com> Cc: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [minor compile fix for SAMA5D2] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
| * | | arm: at91: Add support for gurnardAndre Renaud2016-06-12-0/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This board is based on Snapper 9G45 which has an Atmel AT91SAM9G45 chip and 128MB of SDRAM. It includes a small LCD, 2xUSB host, SD card, Ethernet and two UARTs. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org> [apply CONFIG_BOOTDELAY transition] Signed-off-by: Andreas Bießmann <andreas@biessmann.org>
| * | | at91: Add driver-model GPIO devices for AT91SAM9G45Simon Glass2016-06-12-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add these definitions so that GPIOs can be used with driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | arm: at91: Add a header file for the real-time clockAndre Renaud2016-06-12-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add register definitions for the AT91 RTC so that this can potentially be used in U-Boot. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | arm: at91: dts: Bring in device tree file for AT91SAM9G45Simon Glass2016-06-12-0/+1336
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add this file from Linux v4.5. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | arm: Allow skipping of low-level init with I-cache onSimon Glass2016-06-12-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present CONFIG_SKIP_LOWLEVEL_INIT prevents U-Boot from calling lowlevel_init(). This means that the instruction cache is not enabled and the board runs very slowly. What is really needed in many cases is to skip the call to lowlevel_init() but still perform CP15 init. Add an option to handle this. Reviewed-by: Heiko Schocher <hs@denx.de> Tested-on: smartweb, corvus, taurus, axm Tested-by: Heiko Schocher <hs@denx.de> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
| * | | at91: Add support for the AT91 slow clock controllerAndre Renaud2016-06-12-0/+22
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | This is available on AT91SAM9G45. Add the peripheral address and flag definitions. Signed-off-by: Andre Renaud <andre@designa-electronics.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* | | arm: dra7xx: Assign omap_vcores based on board typeKeerthy2016-06-12-78/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently omap_vcores which holds pmic data is being assigned based on the SoC type. PMIC is not a part of SoC. It is logical to to assign omap_vcores based on board type. Hence over ride the vcores_init function and assign omap_vcores based on the board type. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-06-12-0/+5
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| * | | sunxi: Downclock AHB1 to 100MHz on Allwinner A64Siarhei Siamashka2016-06-10-0/+5
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the AHB1 clock speed is configured as 200MHz by the SPL, but this causes a subtle and hard to reproduce data corruption in SRAM C (for example, this can't be easily detected with a trivial memset/memcmp test). For what it's worth, the Allwinner's BSP configures AHB1 as 200MHz, as can be verified by running the devmem2 tool in the system running the Allwinner's kernel 3.10.x: 0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3180 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x1 However the FEL mode uses more conservative settings (100MHz for AHB1): 0x1C20028: PLL_PERIPH0_CTRL_REG = 0x90041811 0x1C20054: AHB1_APB1_CFG_REG = 0x3190 0x1C20058: APB2_CFG_REG = 0x1000000 0x1C2005C: AHB2_CFG_REG = 0x0 It is yet to be confirmed whether faster AHB1/AHB2 clock settings can be used safely if we initialize the AXP803 PMIC instead of using reset defaults. But in order to resolve the data corruption problem right now, it's best to downclock AHB1 to a safe level. Note that this issue only affects the SPL, which is not fully supported on Allwinner A64 yet and it should not affect the boot0 usage (unless somebody can confirm SRAM C corruption with the boot0 too). Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-06-12-2/+2
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| * | | MIPS: Make CONFIG_SYS_DCACHE_LINE_SIZE int, not hexPaul Burton2016-06-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For consistency with the other cache-related Kconfig entries & the values actually set by boards, make CONFIG_SYS_DCACHE_LINE_SIZE an int entry instead of a hex entry. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Fixes: 372286217f05 ("MIPS: Split I & D cache line size config")
| * | | MIPS: Fix invalidate_dcache_range to operate on L1 DcachePaul Burton2016-06-10-1/+1
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit fb64cda57998 ("MIPS: Abstract cache op loops with a macro") accidentally modified invalidate_dcache_range to operate on the L1 Icache instead of the Dcache. Fix the cache op used to operate on the Dcache. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Fixes: fb64cda57998 ("MIPS: Abstract cache op loops with a macro")
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-06-12-80/+91
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| * | | arm: mxs: Remove misleading commentsMichael Heimpold2016-06-07-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both comments look like being copy & paste errors. Signed-off-by: Michael Heimpold <michael.heimpold@i2se.com> Cc: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com>
| * | | imx: mx7: implement reset_miscPeng Fan2016-05-31-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to power down lcdif to make 'reset' can pass stress test. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | imx-common: timer: support i.MX6DQPlusPeng Fan2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To i.MX6DQPlus, osc can be choosed as the source of gpt, so add i.MX6DQPlus support in gpt_has_clk_source_osc. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | imx-common: sata: return failure if not i.MX6DQPlusPeng Fan2016-05-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX6DQPlus support sata interface, we should not return failure when CPU is i.MX6DQPlus. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | imx-common: hab: support i.MX6DQPlusPeng Fan2016-05-24-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support i.MX6DQPlus, otherwise wrong hab address will be used for i.MX6QDPlus. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
generated by cgit v1.1 at 2024-11-06 18:28:10 +0000