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* MIPS: move au1x00 SoC code to arch/mips/mach-au1x00Daniel Schwierzeck2015-01-30-10/+8
| | | | | | | | | | Move all au1x00 code out of arch/mips/cpu/mips32 to allow unification of CPU code in a later patch. The reorganization of the SoC specific header files will be done in a later patch series. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
* MIPS: handle mips64 ST0_KX bit in mips32 start.SPaul Burton2015-01-30-1/+3
| | | | | | | | | In preparation for sharing a single copy of start.S between mips32 & mips64, handle setting the KX bit of the cop0 Status register when the mips32 start.S is built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: handle mips64 relocs in mips32 start.SPaul Burton2015-01-30-2/+17
| | | | | | | | | In preparation for sharing a single copy of start.S between mips32 & mips64, handle mips64 relocations in the mips32 start.S when built for mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: use asm.h macros in mips32 start.SPaul Burton2015-01-30-55/+61
| | | | | | | | | | | | | | Where the mips32 & mips64 implementations of start.S differ in terms of access sizes & offsets, use the appropriate macros from asm.h to abstract those differences away. This is in preparation for sharing a single copy of start.S between mips32 & mips64. The exception to this is loads of immediates to be written to the cop0 Config register, which is a 32bit register on mips64 and therefore constants written to it can be loaded as such. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* malta: IDE supportPaul Burton2015-01-29-0/+5
| | | | | | | | | This patch adds IDE support to the MIPS Malta board. The IDE controller is enabled after probing the PCI bus and otherwise just makes use of U-boot generic IDE support. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: clear TagLo select 2 during cache initPaul Burton2015-01-29-2/+8
| | | | | | | | | | Current MIPS cores from Imagination Technologies use TagLo select 2 for the data cache. The architecture requires that it is safe for software to write to this register even if it isn't present, so take the trivial option of clearing both selects 0 & 2. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: allow systems to skip loads during cache initPaul Burton2015-01-29-6/+19
| | | | | | | | | | | | | Current MIPS systems do not require that loads be performed to force the parity of cache lines, a simple invalidate by clearing the tag for each line will suffice. Thus this patch makes the loads & subsequent second invalidation conditional upon the CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD option, and defines that for existing mips32 targets. Exceptions are malta where this is known to be unnecessary, and qemu-mips where caches are not implemented. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: inline mips_init_[id]cache functionsPaul Burton2015-01-29-58/+28
| | | | | | | | | | | The mips_init_[id]cache functions are small & only called once from a single callsite. Inlining them allows mips_cache_reset to avoid having to bother moving arguments around & leaves it a leaf function which is thus able to simply keep the return address live in the ra register throughout, simplifying the code. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: refactor cache loops to a macroPaul Burton2015-01-29-17/+13
| | | | | | | | Reduce duplication by performing loops through cache tags using an assembler macro. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: refactor L1 cache config reads to a macroPaul Burton2015-01-29-56/+41
| | | | | | | | | Reduce duplication between reading the configuration of the L1 dcache & icache by performing both using a macro which calculates the appropriate line & cache sizes from the coprocessor 0 Config1 register. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: unify cache initialization codePaul Burton2015-01-29-224/+15
| | | | | | | | | | | | | | The mips32 & mips64 cache initialization code differs only in that the mips32 code supports reading the cache size from coprocessor 0 registers at runtime. Move the more developed mips32 version to a common arch/mips/lib/cache_init.S & remove the now-redundant mips64 version in order to reduce duplication. The temporary registers used are shuffled slightly in order to work for both mips32 & mips64 builds. The RA register is defined differently to suit mips32 & mips64, but will be removed by a later commit in the series after further cleanup. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: unify cache maintenance functionsPaul Burton2015-01-29-167/+119
| | | | | | | | | Move the more developed mips32 version of the cache maintenance functions to a common arch/mips/lib/cache.c, in order to reduce duplication between mips32 & mips64. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* MIPS: avoid .set ISA for cache operationsPaul Burton2015-01-29-38/+33
| | | | | | | | | | | | As a step towards unifying the cache maintenance code for mips32 & mips64 CPUs, stop using ".set <ISA>" directives in the more developed mips32 version of the code. Instead, when present make use of the GCC builtin for emitting a cache instruction. When not present, simply don't bother with the .set directives since U-boot always builds with -march=mips32 or higher anyway. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2015-01-26-145/+535
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| * x86: ivybridge: Drop the Kconfig MRC cache informationSimon Glass2015-01-24-28/+0
| | | | | | | | | | | | This is now stored in the device tree. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: config: Enable hook for saving MRC configurationSimon Glass2015-01-24-0/+5
| | | | | | | | | | | | | | Add a hook to ensure that this information is saved. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Implement a cache for Memory Reference Code parametersSimon Glass2015-01-24-0/+464
| | | | | | | | | | | | | | | | | | | | | | The memory reference code takes a very long time to 'train' its SDRAM interface, around half a second. To avoid this delay on every boot we can store the parameters from the last training sessions to speed up the next. Add an implementation of this, storing the training data in CMOS RAM and SPI flash. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: dts: Add SPI flash MRC details for chromebook_linkSimon Glass2015-01-24-1/+14
| | | | | | | | | | | | | | | | Correct the SPI flash compatible string, add an alias and specify the position of the MRC cache, used to store SDRAM training settings for the Memory Reference Code. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Use ipchecksum from net/Simon Glass2015-01-24-97/+4
| | | | | | | | | | | | | | The existing IP checksum function is only accessible to the 'coreboot' cpu. Drop it in favour of the new code in the network subsystem. Signed-off-by: Simon Glass <sjg@chromium.org>
| * x86: Fix various code format issues in start16.SBin Meng2015-01-23-10/+10
| | | | | | | | | | | | | | | | | | | | | | Various minor code format issues are fixed in start16.S: - U-boot -> U-Boot - 32bit -> 32-bit - Use TAB instead of SPACE to indent - Move the indention location of the GDT comment block Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Test mtrr support flag before accessing mtrr msrBin Meng2015-01-23-2/+19
| | | | | | | | | | | | | | | | | | | | On some x86 processors (like Intel Quark) the MTRR registers are not supported. This is reflected by the CPUID (EAX 01H) result EDX[12]. Accessing the MTRR registers on such processors will cause #GP so we must test the support flag before accessing MTRR MSRs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Save mtrr support flag in global dataBin Meng2015-01-23-6/+14
| | | | | | | | | | | | | | | | CPUID (EAX 01H) returns MTRR support flag in EDX bit 12. Probe this flag in x86_cpu_init_f() and save it in global data. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add missing DECLARE_GLOBAL_DATA_PTR for mtrr.cBin Meng2015-01-23-0/+2
| | | | | | | | | | | | | | | | arch/x86/cpu/mtrr.c has access to the U-Boot global data thus DECLARE_GLOBAL_DATA_PTR is needed. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Fix out of bounds irq handlers accessSebastien Ronsse2015-01-23-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using coreboot-x86_defconfig, the following error occurred prior to this modification: CC arch/x86/lib/interrupts arch/x86/lib/interrupts.c: In function ‘do_irqinfo’: arch/x86/lib/interrupts.c:134:24: error: iteration 16u invokes undefined behavior [-Werror=aggressive-loop-optimizations] if (irq_handlers[irq].handler != NULL) { ^ arch/x86/lib/interrupts.c:133:2: note: containing loop for (irq = 0; irq <= CONFIG_SYS_NUM_IRQS; irq++) { ^ cc1: all warnings being treated as errors scripts/Makefile.build:275: recipe for target 'arch/x86/lib/interrupts.o' failed make[1]: *** [arch/x86/lib/interrupts.o] Error 1 Makefile:1093: recipe for target 'arch/x86/lib' failed make: *** [arch/x86/lib] Error 2 Change-Id: I3572a822081b72ab760f1eb99442e1161d3d167e Signed-off-by: Sebastien Ronsse <sronsse@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Support ROMs on other archsSimon Glass2015-01-23-0/+2
| | | | | | | | | | | | | | | | We shouldn't assume that the VGA ROM can always be loaded at c0000. This is only true on x86 machines. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-atmelTom Rini2015-01-26-1/+21
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| * | ARM: atmel: sama5d4: add usb device initial codeBo Shen2015-01-19-0/+16
| | | | | | | | | | | | Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | ARM: atmel: sama5d4: add usb platform dataBo Shen2015-01-19-1/+1
| | | | | | | | | | | | | | | | | | The SAMA5D4 has the same usb platform data with SAMA5D3 SoC. Signed-off-by: Bo Shen <voice.shen@atmel.com>
| * | arm, arm926ejs: make thumb mode compileableHeiko Schocher2015-01-19-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in thumb mode compiler says for example for arch/arm/lib/cache-cp15.c when enabling CONFIG_SYS_THUMB_BUILD: {standard input}: Assembler messages: {standard input}:373: Error: selected processor does not support Thumb mode `mrc p15,0,r4,c1,c0,0' {standard input}:416: Error: selected processor does not support Thumb mode `mcr p15,0,r3,c2,c0,0' so, if caches are disabled, do not use this command on arm926ejs. used on at91 in SPL, to reduce size of SPL. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblazeTom Rini2015-01-26-5/+51
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| * | | ARM: zynq: List qspi, smc and nand baseaddressesMichal Simek2015-01-26-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Add missing addresses to the list. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: List nand, qspi and jtag boot modesMichal Simek2015-01-26-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Use full boot mode list in SPL. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: slcr: Dont modify the reserved bitsSiva Durga Prasad Paladugu2015-01-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: ddrc: Setup half of memory only for ECC caseMichal Simek2015-01-26-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setup half of memory from ram_size for ECC case. All the time the same board can be configured with or without ECC. Based on ECC case detection use half of memory with the same configuration. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Remove empty lineMichal Simek2015-01-26-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | | ARM: zynq: Enable the Neon instructionsMichal Simek2015-01-26-3/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added the lowlevel_init to enable the Neon instructions. Initially the u-boot was causing undefined instruction exception if loaded through tcl, and working fine if loaded through FSBL. The exception was causing in convertion formula of given time to ticks. It was because, the Neon instructions were disabled and hence causing the undefined exception. In FSBL case, the FSBL was enabling the Neon instructions. Hence, added the lowlevel_init to enable the Neon instructions. Also enable neon instructions for non-xilinx toolchain. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Acked-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-marvellTom Rini2015-01-25-3/+8
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| * | | | ARM: kirkwood: fix cpu info for 6282 device idLuka Perkov2015-01-25-3/+8
| | |_|/ | |/| | | | | | | | | | | | | | | | | | Signed-off-by: Luka Perkov <luka@openwrt.org> Acked-By: Prafulla Wadaskar <prafulla@marvell.com> Acked-by: Stefan Roese <sr@denx.de>
* | | | fsl/ls1021qds: Add deep sleep supporttang yuantian2015-01-24-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add deep sleep support on Freescale LS1021QDS platform. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> [York Sun: Fix conflict in fdt.c] Reviewed-by: York Sun <yorksun@freescale.com>
* | | | ls102xa: fdt: Disable QSPI and DSPI in NOR/NAND/SD bootAlison Wang2015-01-23-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As QSPI/DSPI and IFC are pin multiplexed, QSPI and DSPI are only enabled in QSPI boot, and disabled in other boot modes. IFC is enabled in NOR/NAND/SD boot, and disabled in QSPI boot. This patch will add fdt support for the above rules. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | arm: ls102xa: Update snoop settings for CCI-400Alison Wang2015-01-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CAAM is connected to CCI-400 S0 slave interface. Disable snooping for S0 will cause CAAM self test failure. This patch is to enable snooping for S0 slave interface. These CCI-400 operations are moved to board_early_init_f() to be initialized earlier. For S4 slave interface, issuing of snoop requests and DVM message requests are enabled. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | ARM: HYP/non-sec: Make variable gic_dist_addr as a local onetang yuantian2015-01-23-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Defining variable gic_dist_addr as a globe one prevents some functions, which use it, from being used before relocation which is the case in the deep sleep resume process on Freescale SoC platforms. Besides, we can always get the GIC base address by calling get_gicd_base_address() without referring gic_dist_addr. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | crypto/fsl: Add fixup for crypto nodeRuchika Gupta2015-01-23-170/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Era property is added in the crypto node in device tree. Move the code to do so from arch/powerpc/mpc8xxx/fdt.c to drivers/sec/sec.c so that it can be used across arm and powerpc platforms having crypto node. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> [York Sun: Fix commit message indentation] Reviewed-by: York Sun <yorksun@freescale.com>
* | | | arm: ls102xa: Add dummy gpio.h to enable CONFIG_OF_CONTROLRuchika Gupta2015-01-23-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. It includes <asm/gpio.h> and then <asm/gpio.h> includes <asm/arch/gpio.h>. As a result, all the SoCs that enable CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they do not support GPIO. The right fix would be to split the lib/fdtdec.c to remove dependency on GPIO.This commit adds a dummy <asm/arch/gpio.h> to support OF_CONTROL for LS102x platform. This dummy header will be removed after FDT-GPIO stuff is fixed correctly. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | ls102xa: etsec: Select ge0_clk125 for eTSEC clock muxing as defaultAlison Wang2015-01-23-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reverts to use ge0_clk125 for eTSEC clock muxing. For SAI and CAN which are pin multiplexed with RGMII1 in EC1 of RCW, ge2_clk125 will be used via hwconfig. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | | arm/ls1021a: Add workaround for DDR erratum A008378York Sun2015-01-23-0/+1
|/ / / | | | | | | | | | | | | | | | | | | Internal memory controller counters can reach a bad state after training in DDR4 mode if accumulated ECC or DBI mode is eanbled. Signed-off-by: York Sun <yorksun@freescale.com>
* | | powerpc: remove icecube_5200, Lite5200, cpci5200, mecp5200, pf5200Masahiro Yamada2015-01-23-30/+0
| | | | | | | | | | | | | | | | | | | | | | | | These boards are still non-generic boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* | | powerpc: mpc5xxx: PM520 board supportMasahiro Yamada2015-01-23-4/+0
| | | | | | | | | | | | | | | | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Josef Wagner <Wagner@Microsys.de>
* | | powerpc: mpc5xxx: remove Total5200 board supportMasahiro Yamada2015-01-23-4/+0
| | | | | | | | | | | | | | | | | | This board is still a non-generic board. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | powerpc: ppc4xx: remove PPChameleonEVB, CATcenter boardsMasahiro Yamada2015-01-23-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These boards are still non-generic boards. It is a good thing that we can drop board-specific hack code from drivers/mtd/nand/nand_base.c Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Andrea "llandre" Marson <andrea.marson@dave-tech.it>
generated by cgit v1.1 at 2024-10-25 14:36:52 +0000