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* arm: Use optimized memcpy and memset from linuxMatthias Weisser2011-04-27-2/+437
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using optimized versions of memset and memcpy from linux brings a quite noticeable speed (x2 or better) improvement for these two functions. Here are some numbers for test done with jadecpu | HEAD(1)| HEAD(1)| HEAD(2)| HEAD(2)| | | +patch | | +patch | ---------------------------+--------+--------+--------+--------+ Reset to prompt | 438ms | 330ms | 228ms | 120ms | | | | | | TFTP a 3MB img | 4782ms | 3428ms | 3245ms | 2820ms | | | | | | FATLOAD USB a 3MB img* | 8515ms | 8510ms | ------ | ------ | | | | | | BOOTM LZO img in RAM | 3473ms | 3168ms | 592ms | 592ms | where CRC is | 615ms | 615ms | 54ms | 54ms | uncompress | 2460ms | 2462ms | 450ms | 451ms | final boot_elf | 376ms | 68ms | 65ms | 65ms | | | | | | BOOTM LZO img in FLASH | 3207ms | 2902ms | 1050ms | 1050ms | where CRC is | 600ms | 600ms | 135ms | 135ms | uncompress | 2209ms | 2211ms | 828ms | 828ms | | | | | | Copy 1.4MB from NOR to RAM | 134ms | 72ms | 120ms | 70ms | (1) No dcache (2) dcache enabled in board_init *Does not work when dcache is on Size impact: C version: text data bss dec hex filename 202862 18912 266456 488230 77326 u-boot ASM version: text data bss dec hex filename 203798 18912 266288 488998 77626 u-boot 222712 u-boot.bin Signed-off-by: Matthias Weisser <weisserm@arcor.de>
* OMAP3: BeagleBoard: Enable pullups on i2c2.Steve Kipisz2011-04-27-0/+14
| | | | | | | | | This allows the reading of EEPROMS on the expansion bus without adding external pull-ups. Signed-off-by: Jason Kridner <jkridner@beagleboard.org> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* MX31: drop warnings in get_cpu_revStefano Babic2011-04-27-1/+1
| | | | | | | | Drop warnings due to recent commit ARM: mx31: Print the silicon version Signed-off-by: Stefano Babic <sbabic@denx.de> CC: Fabio Estevam <fabio.estevam@freescale.com>
* MX5: factor out boot cause funciton to common codeJason Liu2011-04-27-0/+28
| | | | | | | factor out boot cause function to common code to avoid the duplicate code in each board support package Signed-off-by: Jason Liu <jason.hui@linaro.org>
* ARM: MX31: Fix file name labelFabio Estevam2011-04-27-3/+3
| | | | | | | | | Commit 5d2c154 (IMX: MX31: Cleanup include files and drop nasty #ifdef in drivers) renamed mx31-imx-regs.h to imx-regs.h. Change the file label accordingly. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX31: Introduce get_reset_cause()Fabio Estevam2011-04-27-1/+28
| | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Detlev Zundel <dzu@denx.de>
* ARM: mx31: Print the silicon versionFabio Estevam2011-04-27-2/+53
| | | | | | | | | | | Use the same method of the Linux kernel to print the MX31 silicon version on boot. Tested on a MX31PDK with a 2.0 silicon, where it shows: CPU: Freescale i.MX31 rev 2.0 at 531 MHz Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* IMX: MX31: Cleanup include files and drop nasty #ifdef in driversStefano Babic2011-04-27-7/+7
| | | | | | | | | | As exception among the i.MX processors, the i.MX31 has headers without general names (mx31-regs.h, mx31.h instead of imx-regs.h and clock.h). This requires several nasty #ifdef in the drivers to include the correct header. The patch cleans up the driver and renames the header files as for the other i.MX processors. Signed-off-by: Stefano Babic <sbabic@denx.de>
* mx25: Make the UART port number explicit in its setup functionFabio Estevam2011-04-27-1/+1
| | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* MX31: add support for MX31 watchdogStefano Babic2011-04-27-1/+47
| | | | | | | | | | | | | | | | | | The patch add CONFIG_HW_WATCHDOG to be used with the internal watchdog timer of the MX31 processor. Two function are exported for the board maintainers: mxc_hw_watchdog_enable mxc_hw_watchdog_reset The board maintainer can decide to use mxc_hw_watchdog_reset as hw_watchdog_reset, or to implement his own function to reset the watchdog. The watchdog timer can be configured with CONFIG_SYS_WD_TIMER_SECS (value in seconds). The MX31 allows values between 0.5 (CONFIG_SYS_WD_TIMER_SECS = 0) and 128 seconds. Signed-off-by: Stefano Babic <sbabic@denx.de>
* Merge branch 'phylib' of git://git.denx.de/u-boot-mmcWolfgang Denk2011-04-20-35/+24
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| * fsl: Change fsl_phy_enet_if to phy_interface_tAndy Fleming2011-04-20-35/+5
| | | | | | | | | | | | | | | | | | | | | | | | The fsl_phy_enet_if enum was, essentially, the phy_interface_t enum. This meant that drivers which used fsl_phy_enet_if to deal with PHY interfaces would have to convert between the two (or we would have to have them mirror each other, and deal with the ensuing maintenance headache). Instead, we switch all clients of fsl_phy_enet_if over to phy_interface_t, which should become the standard, anyway. Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Detlev Zundel <dzu@denx.de>
| * tsec: Convert tsec to use PHY LibAndy Fleming2011-04-20-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | This converts tsec to use the new PHY Lib. All of the old PHY support is ripped out. The old MDIO driver is split off, and placed in fsl_mdio.c. The initialization is modified to initialize the MDIO driver as well. The powerpc config file is modified to configure PHYLIB if TSEC_ENET is configured. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Detlev Zundel <dzu@denx.de>
* | Merge branch 'misc' of git://git.denx.de/u-boot-blackfinWolfgang Denk2011-04-20-119/+53
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| * | gpio: generalize for all generic gpio providersMike Frysinger2011-04-13-119/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Blackfin gpio command isn't terribly Blackfin-specific. So generalize the few pieces into two new optional helpers: name_to_gpio() - turn a string name into a GPIO # gpio_status() - display current pin bindings (think /proc/gpio) Once these pieces are pulled out, we can relocate the cmd_gpio.c into the common directory. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Revert "PowerPC: Add support for -msingle-pic-base"Wolfgang Denk2011-04-20-127/+12
| |/ |/| | | | | | | | | | | This reverts commit 39768f7715ed637ef02f49fc7de664cc1aaf14b3. Reson: it breaks a number of boards with embedded environment as the code size grows in some places.
* | sc520: Move reset to stand-alone fileGraeme Russ2011-04-13-10/+41
| | | | | | | | | | | | | | | | Partial linking allows weak functions to be overridden in files containing only one function. Moving the sc520 override of reset_cpu gets rid of an ugly #ifdef Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | x86: Rename i386 to x86Graeme Russ2011-04-13-12/+12
| | | | | | | | Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | x86: Code cleanupGraeme Russ2011-04-13-176/+166
| | | | | | | | | | | | | | | | | | Make the copyright notices in the x86 files consistent and update them with proper attributions for recent updates Also fix a few comment style/accuracy and whitespace/blank line issues Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | eNET: Remove config.mkGraeme Russ2011-04-13-2/+3
|/ | | | | | | | | | | By including <config.h> in the ld script, CONFIG_SYS_MONITOR_LEN (defined in the boards config file) can be used in lieu of FLASH_SIZE (defined in the board specific config.mk) As this is the last remaining entry in the board specific config.mk, this file can now be removed Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* Make STANDALONE_LOAD_ADDR configurable per boardWolfgang Denk2011-04-12-15/+13
| | | | | | | | | | | | | Rename STANDALONE_LOAD_ADDR into CONFIG_STANDALONE_LOAD_ADDR and allow that the architecture-specific default value gets overwritten by defining the value in the board header file. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Mike Frysinger <vapier@gentoo.org> Cc: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Cc: Daniel Hellstrom <daniel@gaisler.com> Cc: Tsi Chung Liew <tsi-chung.liew@freescale.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Fix misc spelling errors found by lintianLoïc Minier2011-04-12-5/+5
| | | | Signed-off-by: Loïc Minier <loic.minier@linaro.org>
* PowerPC: Add support for -msingle-pic-baseJoakim Tjernlund2011-04-11-12/+127
| | | | | | | | | | | | | -msingle-pic-base is a new gcc option for ppc and it reduces the size of my u-boot with 6-8 KB. While at it, add -fno-jump-tables too to save a few more bytes. -msingle-pic-base will be in gcc 4.6, however backported patches are available at http://bugs.gentoo.org/show_bug.cgi?id=347281 Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* PowerPC: Move -fPIC flag to common placeJoakim Tjernlund2011-04-11-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | The -fPIC flag belongs with -mrelocatable, move it there. Also change -fPIC to -fpic as this produces smaller binaries. However, currently -mrelocatable promotes -fpic to -fPIC, a fix for this is in upcoming gcc 4.6 or you can apply this small patch to gcc: diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h index 8da8410..e4b8280 100644 --- a/gcc/config/rs6000/sysv4.h +++ b/gcc/config/rs6000/sysv4.h @@ -227,7 +227,8 @@ do { \ } \ \ else if (TARGET_RELOCATABLE) \ - flag_pic = 2; \ + if (!flag_pic) \ + flag_pic = 2; \ } while (0) #ifndef RS6000_BI_ARCH -- Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2011-04-10-80/+147
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| * powerpc/85xx: Removed clearing of L2-as-SRAMFabian Cenedese2011-04-10-7/+0
| | | | | | | | | | | | | | | | Removed clearing of L2 cache as SRAM as it is not necessary without ECC. This also speeds up the booting process. Signed-off-by: Fabian Cenedese <cenedese@indel.ch> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl_esdhc: Deal with watermark level register related changesPriyanka Jain2011-04-10-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add PBL boot from SPI flash support on P4080DSShaohui Xie2011-04-10-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | PBL(pre-boot loader): SPI flash used as RCW(Reset Configuration Word) and PBI(pre-boot initialization) source, CPC(CoreNet Platform Cache) used as 1M SRAM where PBL will copy whole U-BOOT image to, U-boot can boot from CPC after PBL completes RCW and PBI phases. Signed-off-by: Chunhe Lan <b25806@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add support usb2/etsec and tdm/audio pin multiplex on P1022DSJiang Yutang2011-04-10-0/+10
| | | | | | | | | | | | | | | | | | | | | | For soc which have pin multiplex relation, some of them can't enable simultaneously. This patch add environment var 'hwconfig' content defination for them. you can enable some one function by setting environment var 'hwconfig' content and reset board. Detail setting please refer doc/README.p1022ds Signed-off-by: Jiang Yutang <b14898@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * p4080ds: remove rev1-specific code for the SERDES8 erratumTimur Tabi2011-04-10-59/+47
| | | | | | | | | | | | | | | | Remove the SERDES8 erratum work-around code that only applied to P4080 rev1, which is not supported by this version of U-Boot. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: rename NAND prefixes to CONFIG_SYSMatthew McClintock2011-04-08-4/+4
| | | | | | | | | | | | | | | | | | | | renaming 85xx define CONFIG_NAND_OR_PRELIM to CONFIG_SYS_NAND_OR_PRELIM and CONFIG_NAND_BR_PRELIM to CONFIG_SYS_NAND_BR_PRELIM to use the more appropriate CONFIG_SYS prefix as well as be consistent with 83xx. Signed-off-by: Matthew McClintock <msm@freescale.com> cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add some defines & registers in immap_85xx.hZhao Chenhui2011-04-05-1/+6
| | | | | | | | | | | | | | | | | | * Added SDHCDCR register to GUR struct * Added SDHCDCR_CD_INV define related to SDHCDCR * Added Pin Muxing define related to TDM on P102x Signed-off-by: Zhao Chenhui <b35336@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: Add P1021 specific QE and UEC supportHaiying Wang2011-04-05-10/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | P1021 has some QE pins which need to be set in pmuxcr register before using QE functions. In this patch, pin QE0 and QE3 are set for UCC1 and UCC5 in Eth mode. QE9 and QE12 are set for MII management. QE12 needs to be released after MII access because QE12 pin is muxed with LBCTL signal. Also added relevant QE support defines unique to P1021. The P1021 QE is shared on P1012, P1016, and P1025. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * powerpc/85xx: don't init SDRAM when CONFIG_SYS_RAMBOOTZhao Chenhui2011-04-05-0/+12
| | | | | | | | | | | | Signed-off-by: Zhao Chenhui <b35336@freescale.com> Acked-by: Li Yang <leoli@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Blackfin: replace "bfin_reset_or_hang()" with "panic()"Kyle Moffett2011-04-08-19/+2
| | | | | | | | | | | | | | | | | | | | | | The bfin_reset_or_hang function unnecessarily duplicates the panic() logic based on CONFIG_PANIC_HANG. This patch deletes 20 lines of code and just calls panic() instead. This also makes the following generic-restart conversion patch simpler. Signed-off-by: Kyle Moffett <Kyle.D.Moffett@boeing.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: bootrom.h: sync with toolchainMike Frysinger2011-04-08-27/+59
| | | | | | | | | | | | We need the updated LDR bit defines for our LDR utils. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: default to L1 bank A when L1 bank B does not existMike Frysinger2011-04-08-3/+7
| | | | | | | | | | | | | | Some parts lack Bank B in L1 data, so have the linker script fall back to Bank A when that happens. This way we can still leverage L1 data. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: turn off caches when self initializingMike Frysinger2011-04-08-12/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When bootstrapping ourselves on the fly at runtime (via "go"), we need to turn off the caches to avoid taking software exceptions. Since caches need CPLBs and CPLBs need exception handlers, but we're about to rewrite the code in memory where those exception handlers live, we need to turn off caches first. This new code also encourages a slight code optimization by storing the MMR bases in dedicated registers so we don't have to fully load up the pointer regs multiple times. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: only check for os log when we have external memoryMike Frysinger2011-04-08-1/+1
| | | | | | | | | | | | | | | | If the part has no external memory configured, then there will be no os log for us to check, and any attempt to access that memory will trigger hardware errors. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: BF537: unify duplicated headersMike Frysinger2011-04-08-2446/+2419
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: BF52x: unify duplicated headersMike Frysinger2011-04-08-2068/+1481
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: drop duplicate system mmr and L1 scratch definesMike Frysinger2011-04-08-42/+1
| | | | | | | | | | | | | | Common code already takes care of setting up these defines when a port hasn't specified them, so punt the duplicate values. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: BF50x: new processor portMike Frysinger2011-04-08-17/+3193
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: fix bd_t handlingMike Frysinger2011-04-08-9/+6
| | | | | | | | | | | | | | | | | | The recent global data changes (making the size autogenerated) broke the board info handling on Blackfin ports as we were lying and lumping the bd_t size in with the gd_t size. So use the new dedicated bd_t size to setup its own address in memory. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: bf537: fix L1 data definesMike Frysinger2011-04-08-1/+1
| | | | | | | | | | | | | | The __BFIN_DEF_ADSP_BF537_proc__ define isn't setup anymore, so use the one coming from the compiler. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: serial: clean up muxing a bitMike Frysinger2011-04-08-31/+20
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: move CONFIG_BFIN_CPU back to board config.hMike Frysinger2011-04-08-2/+13
| | | | | | | | | | | | This is a revert of 821ad16fa9900c as Wolfgang doesn't like the new code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: unify bootmode based LDR_FLAGS setupMike Frysinger2011-04-08-0/+3
| | | | | | | | | | | | Unify this convention for all Blackfin boards. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: drop CONFIG_SYS_TEXT_BASE from boardsMike Frysinger2011-04-08-0/+4
| | | | | | | | | | | | | | We don't want/use this value for Blackfin boards, so punt it and have the common code error out when people try to use it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: skip RAM display for 0 mem systemsMike Frysinger2011-04-08-2/+5
|/ | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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