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| * | | | Add TI816X supportTENART Antoine2013-08-15-117/+1076
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Fix warnings about vtp things in emif4.c, adapt AM43XX] Signed-off-by: Tom Rini <trini@ti.com>
| * | | | Prepare for TI816X : reuse existing code from TI814XTENART Antoine2013-08-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename some CONFIG_TI814X to a more generic CONFIG_TI81XX Signed-off-by: Antoine Tenart <atenart@adeneo-embedded.com> [trini: Adapt for CONFIG_OMAP_COMMON changes, AM43XX] Signed-off-by: Tom Rini <trini@ti.com>
| * | | | arm, da850: enable the correct uart in arch_cpu_init()Heiko Schocher2013-08-15-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in arch_cpu_init() uart2 is fix enabled, without reference the setting from CONFIG_SYS_NS16550_COM1. Use the setting from CONFIG_SYS_NS16550_COM1 for enabling the console. Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Tom Rini <tom.rini@gmail.com> Cc: Christian Riesch <christian.riesch@omicron.at>
| * | | | arm/davinci/da850: add uart0_pins_rtscts and RMII_MHz_50_CLK in ↵Heiko Schocher2013-08-15-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | emac_pins_rmii pinmux Signed-off-by: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@ti.com>
| * | | | arm: spl: For Falcon Mode, set a default machid of ~0Tom Rini2013-08-15-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With device trees, boards do not always set CONFIG_MACH_TYPE now, so we must not rely on this define being set. The kernel uses ~0 to see if we have a valid machine number or not, so set that as the default, invalid machine, id and only fix if CONFIG_MACH_TYPE is set. Acked-by: Dan Murphy <dmurphy@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Tom Rini <trini@ti.com>
| * | | | omap: emif: Set initial DDR PHY config firstTaras Kondratiuk2013-08-15-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit "OMAP5: emif/ddr: Change emif settings as required for ES1.0 silicon" (f40107345cbcd6e0d1747eda45e76c4e2a6df0db) changed sequence to set final DDR PHY config register value at the beginning. Looks like it was made by mistake and should be reverted. Signed-off-by: Taras Kondratiuk <taras@ti.com>
| * | | | ARM: omap24xx: remove remainders of dead boardMasahiro Yamada2013-08-15-193/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since Commit 7f5eef9 removed OMAP2420H4 support, arm1136/omap24xx has not been used at all. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | | ARM: omap3: Implement dpll5 (HSUSB clk) workaround for OMAP36xx/AM/DM37xx ↵Naumann Andreas2013-08-15-1/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | according to errata sprz318e. In chapter 'Advisory 2.1 USB Host Clock Drift Causes USB Spec Non-compliance in Certain Configurations' of the TI Errata it is recommended to use certain div/mult values for the DPLL5 clock setup. So far u-boot used the old 34xx values, so I added the errata recommended values specificly for 36xx init only. Also, the FSEL registers exist no longer, so removed them from init. Tested this on a AM3703 board with 19.2MHz oscillator, which previously couldnt lock the dpll5 (kernel complained). As a consequence the EHCI USB port wasnt usable in U-Boot and kernel. With this patch, kernel panics disappear and USB working fine in u-boot and kernel. Signed-off-by: Andreas Naumann <anaumann@ultratronik.de> [trini: Add extern to <asm/arch-omap3/clock.h> Signed-off-by: Tom Rini <trini@ti.com>
| * | | | ARM: AM43xx: Add build supportLokesh Vutla2013-08-15-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add AM43xx support in the required places Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | | ARM: OMAP: Add CONFIG_OMAP_COMMONLokesh Vutla2013-08-15-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding a new CONFIG_OMAP_COMMON which is included by all boards that needs to build cpu/armv7/omap-common folder. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | | ARM: AM43xx: clocks: Add dpll and clock dataLokesh Vutla2013-08-15-1/+116
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add dpll and clock data for AM43xx Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | | ARM: AM43xx: Add header filesLokesh Vutla2013-08-15-20/+378
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the following data: -> Prcm structure -> Base addresses -> Pin mux structure. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | | ARM: AM33xx: Move s_init to a common placeHeiko Schocher2013-08-15-10/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | s_init has the same outline for all the AM33xx based board. So making it generic. This also helps in addition of new Soc with minimal changes. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | | | ARM: AM33xx: Cleanup clocks layerLokesh Vutla2013-08-15-219/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cleaning up the clocks layer. This helps in addition of new Soc with minimal changes. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | | | ARM: AM33xx: Cleanup dplls dataLokesh Vutla2013-08-15-182/+227
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Locking sequence for all the dplls is same. In the current code same sequence is done repeatedly for each dpll. Instead have a generic function for locking dplls and pass dpll data to that function. This is derived from OMAP4 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Heiko Schocher <hs@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
| * | | am335x_evm: Add support to boot from NOR.Steve Kipisz2013-07-30-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NOR requires that s_init be within the first 4KiB of the image so that we can perform the rest of the required pinmuxing to talk with the rest of NOR that we are found on. When NOR_BOOT is set we save our environment in NOR at 512KiB and a redundant copy at 768KiB. We avoid using SPL for this case and u-boot.bin is written directly to the start of NOR. We enclose the DMM-related parts of arch/arm/cpu/armv7/am33xx/emif4.c with TI81xx checks as at this time U-Boot does not discard unused sections in the main build and this code relies on functions specific to (and only provided in) ti81xx-related code. Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> Signed-off-by: Tom Rini <trini@ti.com>
| * | | am335x_evm: Add support for the NOR module on the memory capeSteve Kipisz2013-07-30-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the NOR module that attaches to the memory cape for a Beaglebone board. This does not add booting support; only support so that you can boot from SD/MMC and see the NOR module so that it can be programmed. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com> [trini: Clean up config changes slightly] Signed-off-by: Tom Rini <trini@ti.com>
| * | | am33xx: Correct gpmc_cfg->irqstatus/enableTom Rini2013-07-30-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on our usage of the GPMC, either with NOR or NAND we do not need to be setting the irqstatus or irqenable bits and should clear them like we have historically. Signed-off-by: Tom Rini <trini@ti.com>
| * | | ARM: DRA7xx: Add CPSW support to DRA7xx EVMMugunthan V N2013-07-26-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | Adding support for CPSW Ethernet support found in DRA7xx EVM Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | | ARM: DRA7xx: Enable GMAC clock controlMugunthan V N2013-07-26-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | Enabling CPSW module by enabling GMAC clock control Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | | ARM: DRA7xx: Lock DPLL_GMACLokesh Vutla2013-07-26-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Locking DPLL_GMAC [mugunthanvnm@ti.com:Configure only if CPSW is selected] Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
| * | | omap3/sys_info: fix printout of OMAP36XX L3 freqencyAndreas Bießmann2013-07-26-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP36xx/OMAP37xx family uses L3 frequency of 200MHz instead of 165MHz used by OMAP34xx/OMAP35xx. Also fix checkpatch warning about alignment. Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | | arm: omap3: spl: Fix problem with 8bit NAND devicesStefan Roese2013-07-26-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently in OMAP3 SPL, the GPMC for NAND is configured for 16bit access. This patch adds support for 8bit NAND devices as well. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Tom Rini <trini@ti.com>
| * | | Merge branch 'u-boot/master' into u-boot-arm/masterAlbert ARIBAUD2013-07-25-25573/+2238
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| * | | | ARM: highbank: avoid bss write in timer_initRob Herring2013-07-25-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer_init function is called before relocation and writes to bss data were corrupting relocation data. Fix this by removing the call to reset_timer_masked. The initial timer count should be 0 or near 0 anyway, so initializing the variables are not needed. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | | ARM: highbank: set timer prescaler to 256Rob Herring2013-07-25-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 150MHz clock rate gives u-boot time functions problems and there's no benefit to a fast clock, so lower the rate. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | | ARM: highbank: fix get_tbclk value to timer rateRob Herring2013-07-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | get_tbclk should return the timer's frequency, not CONFIG_SYS_HZ. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | | ARM: move interrupt_init to before relocationRob Herring2013-07-25-2/+1
| | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | interrupt_init also sets up the abort stack, but is not setup before relocation. So any aborts during relocation will hang and not print out any useful information. Fix this by moving the interrupt_init to after the stack setup in board_init_f. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
* | | | powerpc/usb: Depricate usb_phy_type and usb_dr_mode uboot env variablesramneek mehresh2013-08-14-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove getting values of usb mode and phy_type from "usb_dr_mode" and "usb_phy_type" uboot env variables. Now, these are determined only from hwconfig string Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | | | fsl/usb: Move USB internal phy definitions to fsl_usb.hramneek mehresh2013-08-14-51/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fsl_usb.h file created to share data bewteen usb platform code and usb ip driver. Internal phy structure definitions moved to this file Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | | | powerpc/mpc85xx:Avoid hardcoded init for serdes block 1 & 2Prabhakar Kushwaha2013-08-14-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not necessary for all processor to have serdes block 1 & 2. They may have only one serdes block. So, put serdes block 1 & 2 related code under defines Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
* | | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2013-08-13-40/+396
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| * | | | powerpc/mpc85xx: Cleanup license header in source filesYork Sun2013-08-12-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the license header introduced by the following patches Add TWR-P10xx board support Add T4240EMU target IDT8T49N222A configuration code Add C29x SoC support Add support for C29XPCIE board Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | 83xx/pcie: fix build error for 83xx pcieRoy Zang2013-08-09-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the following build error caused by patch "powerpc/pcie: add PCIe version 3.x support": pcie.c:302:34: error: 'PCI_LTSSM' undeclared (first use in this function) pcie.c:303:15: error: 'PCI_LTSSM_L0' undeclared (first use in this function) Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc8xxx: Fix TIMING_CFG_3[EXT_ACTTOPRE]James Yang2013-08-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TIMING_CFG_3[EXT_ACTTOPRE] register field is 2 bits wide, but the mask omitted the LSB. This patch provides a 2-bit wide mask. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/85xx: Add C29x SoC supportMingkai Hu2013-08-09-0/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features: - 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Po Liu <Po.Liu@freescale.com>
| * | | | powerpc/pcie: remove PCIe version 3.x define for B4860 and B4420Zang Roy-R619112013-08-09-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | B4860 and B4420 has PCIe version 2.4 IP instead of 3.x Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| * | | | powerpc/pcie: add PCIe version 3.x supportZang Roy-R619112013-08-09-2/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T4240 PCIe IP is version 3.0 and has some update comparing previous QorIQ products. 1. Move Freescale specific register define to arch/powerpc/include/asm/fsl_pci.h and update the register offset define for T4240. 2. add the status/control register define use status/control register to judge the link status 3. The original code uses 'Programming Interface' field to judge if PCIE is EP or RC mode, however, T4240 does not support this functionality. According to PCIE specification, 'Header Type' offset 0x0e is used to indicate header type, so for PCIE controller, the patch changes code to use 'Header Type' field to identify if the PCIE is RC or EP mode. This patch fixes the PCIe card link up issue on T4240QDS. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/rman: fix RMan support for t4240 and b4860Minghuan Lian2013-08-09-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add CONFIG_SYS_DPAA_RMAN macro to t4240 and b4860. 2. Decrease RMan liodn offset number. SET_RMAN_LIODN() is used to set liodn offset of RMan blocks 0-3. For t4240 and b4860, RMan liodn base is assigned to 922, the original offset number is too large that the liodn (base+offset 922+678 = 1600) is greater than 0x500 the maximum liodn number. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.hShaveta Leekha2013-08-09-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It allows files not in the same path to use this function as required by B4 board file Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
| * | | | powerpc/mpc85xx: Add defines for serdes RSTCTL registerShaveta Leekha2013-08-09-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also change the define name SRDS_RSTCTL_SDPD to SRDS_RSTCTL_SDEN, which stands for SerDes enable as mentioned in SerDes module guide Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
| * | | | board/bsc9132qds: Configure DSP DDR controllerPriyanka Jain2013-08-09-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9132 SoC has two separate DDR controllers for PowerPC side and DSP side DDR. They are mapped to PowerPC and DSP CCSR space respectively. BSC9132QDS has two on-board MC34716EP DDR3 memory one connected to PowerPC and other to DSP side controller. Configure DSP DDR controller similar to PowerPC side DDR controller as memories are exactly similar. Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | | board/bsc9132qds: Add DSP side tlb and lawsPriyanka Jain2013-08-09-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BSC9132QDS is a Freescale Reference Design Board for BSC9132 SoC which is a integrated device that contains two powerpc e500v2 cores and two DSP starcores. To support DSP starcore -Creating LAW and TLB for DSP-CCSR space. -Creating LAW for DSP-core subsystem M2 and M3 memory -Creating LAW for 1GB DDR which is connected exclusively to DSP-cores Signed-off-by: Manish Jaggi <manish.jaggi@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Acked-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/srio-pcie-boot: Avoid the NOR_BOOT macro when boot from SRIO/PCIELiu Gang2013-08-09-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a board (slave) boots from SRIO/PCIE, it would get the instructions from a remote board (master) by SRIO/PCIE interface, and the slave's u-boot image should be built with the SYS_TEXT_BASE=0xFFF80000; So the u-boot of the slave should avoid the NOR_BOOT branch at the booting stage. For example, when a P2041RDB boots from SRIO/PCIE, it will set TLB entry 15 from base address "CONFIG_SYS_MONITOR_BASE & 0xffc00000", and with the 4M size as the boot window in NOR_BOOT branch. Because the CONFIG_SYS_MONITOR_BASE = CONFIG_SYS_TEXT_BASE = 0xFFF80000, so the TLB entry will be from base address 0xffc00000 and with 4M size. Then the u-boot will set TLB entry 14 from base address "CONFIG_SYS_INIT_RAM_ADDR", and with the 16K size as the initial stack window. For the P2041RDB platform, the CONFIG_SYS_INIT_RAM_ADDR = 0xffd00000. So the TLB entry 14 and 15 will be in confliction. There will be right TLB entries configurations when avoid the NOR_BOOT branch and set the boot window from 0xfff00000 with 1M size space. Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
| * | | | powerpc/mpc85xx: Workaround for A-005812York Sun2013-08-09-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Erratum A-005812 Incorrect reservation clearing in Write Shadow mode can result in invalid atomic operations. For u-boot, this erratum only impacts SoCs running in write shadow mode. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc8xxx: Add memory reset controlYork Sun2013-08-09-13/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | JEDEC spec requires the clocks to be stable before deasserting reset signal for RDIMMs. Clocks start when any chip select is enabled and clock control register is set. This patch also adds the interface to toggle memory reset signal if needed by the boards. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc8xxx: Add x4 DDR device supportYork Sun2013-08-09-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On selected platforms, x4 DDR devices can be supported. Using x4 devices may lower the performance, but generally they are available for higher density. Tested on MT36JSF2G72PZ-1G9E1 RDIMM. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/mpc8xxx: Set inactive csn_bnds to 0xffffffffYork Sun2013-08-09-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When chip select interleaving is enabled, cs0_bnds is used for address binding. Other csn_bnds are not used. When two controllers interleaving is enabled, cs0_bnds of both controllers are used, other csn_bnds are not. However, the unused csn_bnds may be used internally for calculating addresses for calibration. Setting those registers to 0 may confuse controllers in some cases. Instead, setting them to 0xffffffff together with normal LAWs will guarantee the address is not mapped to DDR. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | powerpc/corenet: Move RCW print to cpu.cYork Sun2013-08-09-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The RCW print is common for all corenet platforms. Not necessary to ducplicate in each board file. Signed-off-by: York Sun <yorksun@freescale.com>
| * | | | mpc85xx: Base emulator supportYork Sun2013-08-09-1/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prepare for emulator support for mpc85xx parts. Disable DDR training and skip wrlvl_cntl_2 and wrlvl_cntl_3 registers. These two registers improve stability but not supported by emulator. Add CONFIG_FSL_TBCLK_EXTRA_DIV for possible adjustment to time base. Signed-off-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-10-31 07:15:24 +0000