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| | * avr32: use dlmalloc for DMA buffersAndreas Bießmann2015-02-17-52/+6
| | | | | | | | | | | | Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
| * | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-02-17-119/+164
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| | * | sunxi: Support the FEL boot mode in the regular u-boot buildSiarhei Siamashka2015-02-16-10/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So that the CONFIG_SPL_FEL option is not needed anymore. And the regular SPL binary, generated by the default u-boot build, is now also bootable over USB in the FEL mode. The SPL still can boot from the SD card too. A bunch of system registers need to be saved/restored in order to ensure that the IRQ handler still works in the BROM FEL code after getting control back from the SPL. This is done in the sunxi code instead of abusing ifdefs in 'start.S'. The decision whether to load the main u-boot binary from the SD card or return to the FEL code in the BROM is done at runtime. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> [hdegoede@redhat.com: Since we now restore various regs before returning to the FEL BROM code we can drop the sunxi specific #ifdefs in start.S] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * | sunxi: Normalise FEL supportSimon Glass2015-02-16-88/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sunxi's FEL code fit with the normal U-Boot boot sequence instead of creating its own. There are some #ifdefs required in start.S. Future work will hopefully remove these. This series is available at u-boot-dm, branch sunxi-working. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * | arm: spl: Provide for a board-specific loaderSimon Glass2015-02-16-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards have a special way of loading U-Boot that does not fit with the existing SPL code. For example sunxi uses an 'FEL' mode where U-Boot is loaded over USB. Add a CONFIG option and boot mode for this. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * | arm: Allow lr to be saved by board codeSimon Glass2015-02-16-5/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The link register value can be required on some boards (e.g. FEL mode on sunxi) so use a branch instruction to jump to save_boot_params() instead of a branch link. This requires a branch back to save_boot_params_ret so adjust the users to deal with this. For exynos just drop the function since it doesn't do anything. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| | * | sunxi: dram: Un-inline dram helper functionsHans de Goede2015-02-16-26/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the dram helper functions to a separate C file, rather then having them as inline helpers in dram.h. This saves 144 bytes in the .text segment for sun6i builds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | ARM: lpc3250: config: add generic board supportVladimir Zapolskiy2015-02-16-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The only LPC3250 board works fine with enabled generic board support, add CONFIG_SYS_GENERIC_BOARD right into the arch config header. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
| * | | keystone2: ddr3: eliminate using global ddr3_size variableVitaly Andrianov2015-02-16-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | KS2 ddr3 initialization uses ddr3_size global variable before u-boot relocation. Even if the variable is not being used after relocation, writing to it corrupts relocation table. This patch removes the global ddr3_size variable and uses local one instead. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Tested-by: Nishanth Menon <nm@ti.com>
| * | | clock_am43xx:Set the MAC clock to /5 for OPP100Steve Kipisz2015-02-16-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When EMAC is in the boot order, the boot ROM sets OPP50 and the MAC clock is set to /2. SPL needs to change it to /5 for Ethernet to generate the correct txclk. This patch sets it correctly. Signed-off-by: Steve Kipisz <s-kipisz2@ti.com>
| * | | ARM: DRA7-evm: DDR3: Update leveling valuesLokesh Vutla2015-02-16-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the software leveling parameters. This fixes the random crash seen on DRA7-evm. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA7: EMIF: Update SDRAM_REF_CTRL register valueLokesh Vutla2015-02-16-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The value in SDRAM_REF_CTRL controls the delay time between the initial rising edge of DDR_RESETn to rising edge of DDR_CKE (JEDEC specs this as 500us). In order to achieve this, SDRAM_REF_CTRL should be written with a value corresponding to 500us delay before starting DDR initialization sequence, and configure proper value at the end of sequence. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | | ARM: DRA72x: DDR3: Fix EMIF timings for 666MHz clockAngela Stegmaier2015-02-16-8/+8
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | DDR3 timing and latency paramenters were not configured correctly for 666MHz. Fixing the timing and latency values according to Data sheet. This fixes the random crashes seen on DRA72-evm. Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * | Merge branch 'sandbox' of git://git.denx.de/u-boot-x86Tom Rini2015-02-16-28/+10
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| | * | sandbox: Adjust the order of the NO_SDL checkSimon Glass2015-02-15-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | An option is provided to avoid using SDL in U-Boot sandbox (and drop support for the LCD). However the check in the Makefile is too late and warnings are printed even if NO_SDL=y is given. Adjust the order to avoid this warning. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| | * | sandbox: Return '-c command' exit value as sandbox exit codeJoe Hershberger2015-02-15-22/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When a command is passed into sandbox using the '-c' argument the command is run directly. This is most helpful when running tests (such as test-dm.sh). Previously the exit code was an unused enum. Change it to be the actual return code from the command so that the script calling sandbox can know if the command succeeded (tests passed). Also remove the now completely unused "exit_state" in sandbox. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | Merge git://git.denx.de/u-boot-samsungTom Rini2015-02-13-325/+338
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| | * | Exynos: Clock: Cleanup soc_get_periph_rateAkshay Saraswat2015-02-13-39/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we have src, div and pre-div mask bits defined corresponding to peripherals, calculation of clock specific to I2C appears redundant and confusing. Using clk_bit_info struct we can write calculations generic to all peripherals which makes code easy to understand and free from peripheral specific exceptions. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos: clock: change mask bits as per peripheralAkshay Saraswat2015-02-13-73/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have assumed and kept mask bits for divider and pre-divider as 0xf and 0xff, respectively. But these mask bits change from one peripheral to another, and hence, need to be specified in accordance with the peripherals. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos5: Use clock_get_periph_rate generic APIAkshay Saraswat2015-02-13-235/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replacing SoC and peripheral specific function calls with generic clock_get_periph_rate calls to get the peripheral clocks. Also, removing dead code of peripheral and SoC specific function implementations which was used earlier for fetching peripheral clocks. This code is not being used anymore because of the introduction of generic clock_get_periph_rate function. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos5: Fix exynos5_get_periph_rate calculationsAkshay Saraswat2015-02-13-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | exynos5_get_periph_rate function reads incorrect div for SDMMC2 & 3. It also reads prediv and does division only for SDMMC0 & 2 when actually various other peripherals need that. Adding changes to fix these mistakes in periph rate calculation. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos542x: Add and enable get_periph_rate supportAkshay Saraswat2015-02-13-7/+150
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We planned to fetch peripheral rate through one generic API per peripheral. These generic peripheral functions are in turn expected to fetch apt values from a function refactored as per SoC versions. This patch adds support for fetching peripheral rates for Exynos5420 and Exynos5800. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos542x: Move exynos5420_get_pll_clk up and renameAkshay Saraswat2015-02-13-41/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moving exynos5420_get_pll_clk function definition up in the code to keep it together with rest of SoC_get_pll_clk functions. This makes code more legible and also removes the need of declaration when called before the position of definition in code. Also, renaming exynos5420_get_pll_clk to exynos542x_get_pll_clk because it is being used for both Exynos 5420 and 5800. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Exynos5: Fix compiler warnings due to clock_get_periph_rateAkshay Saraswat2015-02-13-31/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently, members of clk_bit_info array do not map correctly to the members of enum periph_id. This mapping got broken after we changed periph_id(s) to reflect interrupt number instead of their position in a sequence. This patch intends to fix above mentioned issue. Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | EXYNOS5: Add function to enable exynos5420 usbdev phy ctrlJoonyoung Shim2015-02-13-2/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Exynos5420 has different registers with other exynos5 SoCs to control usb device phy, so need separated function to enable exynos5420 usb device phy. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Odroid-XU3: Add eMMC-reset node on DTJoonyoung Shim2015-02-13-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This needs for special handling of nRESET_OUT line(GPD1-0 gpio) for eMMC memory to perform complete reboot on Odroid XU3 board. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | Odroid: Add eMMC-reset node on DTJoonyoung Shim2015-02-13-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This needs for special handling of nRESET_OUT line(GPK1-2 gpio) for eMMC memory to perform complete reboot on Odroid X2/U3 boards. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| | * | arm: exynos: fix the div value for set_mmc_clkJaehoon Chung2015-02-13-0/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The most exynos used the "Ratio + 1" as div value. And value at register is "Ratio". So if want to set exact value, it needs to subtract one. Value at register ("Ratio") = div - 1 Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Merge git://git.denx.de/u-boot-dmTom Rini2015-02-13-15/+1667
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| | * | dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN to KconfigSimon Glass2015-02-12-0/+30
| | | | | | | | | | | | | | | | | | | | Move this option to Kconfig and update all boards. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | dm: at91: Drop use of ATMEL_PIO_PORTS in the header fileSimon Glass2015-02-12-8/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With driver model the number of PIO ports is defined by platform data, so remove it from the header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andreas Bießmann <andreas.devel@googlemail.com>
| | * | dm: sandbox: Move driver model CONFIGs to KconfigSimon Glass2015-02-12-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | dm: omap3: Move driver model CONFIGs to KconfigSimon Glass2015-02-12-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | dm: tegra: Move driver model CONFIGs to KconfigSimon Glass2015-02-12-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | dm: x86: Move driver model CONFIGs to KconfigSimon Glass2015-02-12-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | dm: exynos: Move driver model CONFIGs to KconfigSimon Glass2015-02-12-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove driver model CONFIGs from the board config headers and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | dm: Move Raspberry Pi driver model CONFIGs to KconfigSimon Glass2015-02-12-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove driver model CONFIGs from the board config header and use Kconfig instead. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | powerpc: ppc4xx: Add defaults for DT based booting to really workStefan Roese2015-02-12-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These additional nodes need to be provided to get U-Boot to boot correctly on the Canyonlands / Glacier board: - chosen path to the console-uart - reg-shift set to 0 in the uart device nodes Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | powerpc: Add linkage.h fileSimon Glass2015-02-12-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | This permits us to use linux/linkage.h on PowerPC machines. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | ppc: amcc: Omit unneeded ns16550 CONFIG if using driver modelSimon Glass2015-02-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This comes from the device tree or a call to get_uart_clock(). Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | powerpc: ppc4xx: Allow the end of u-boot.bin to be foundSimon Glass2015-02-12-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define an _end symbol indicating the end of u-boot.bin. Also add some dummy words into the link script to ensure that u-boot.bin will always extend that far. There may be a better way of doing this. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | powerpc: ppc4xx: Add a gpio.h header fileSimon Glass2015-02-12-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is required at present for device tree control. The ppc4xx does support GPIOs but does not seem to have a proper driver. So this file is empty. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | powerpc: ppc4xx: Call board_init_f_mem() for generic boardSimon Glass2015-02-12-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | Call this function to set up our early memory. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | powerpc: ppc4xx: dts: Bring in canyonlands device tree filesSimon Glass2015-02-12-0/+1484
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The canyonlands.h config file works with canyonlands, glacier and arches boards. Bring in the device tree files for these from Linux 3.17. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | powerpc: ppc4xx: canyonlands: Move to generic boardSimon Glass2015-02-12-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Switch to generic board so that this board will not be broken/removed. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | powerpc: ppc4xx: Add ramboot config for glacierSimon Glass2015-02-12-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new ramboot config for glacier so that it is possible to test U-Boot loaded over Ethernet instead of using JTAG. Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | powerpc: ppc4xx: canyonlands: config: Tidy up CONFIGs and config.mkSimon Glass2015-02-12-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many CONFIG options have an unnecessary value of 1. CONFIG_440 is set in the various board config files. Also simplify the CONFIG_440 check in config.mk Signed-off-by: Simon Glass <sjg@chromium.org>
| | * | powerpc: Permit device tree control of U-Boot (CONFIG_OF_CONTROL)Simon Glass2015-02-12-0/+1
| | |/ | | | | | | | | | | | | | | | | | | Enable this in the Kconfig so that PowerPC boards can use device tree to configure U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | Merge git://git.denx.de/u-boot-arcTom Rini2015-02-13-3/+335
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| | * | arc: introduce U-Boot port for ARCv2 ISAAlexey Brodkin2015-02-13-3/+335
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARC HS and ARC EM are new cores based on ARCv2 ISA which is binary incompatible with ISAv1 (AKA ARCompact). Significant difference between ISAv2 and v1 is implementation of interrupt vector table. In v1 it is implemented in the same way as on many other architectures - as a special location where user may put whether code executed in place (if machine word of space is enough) or jump to a full-scale interrupt handler. In v2 interrupt table is just an array of adresses of real interrupt handlers. That requires a separate section for IVT that is not encoded as code by assembler. This change adds support for following cores: * ARC EM6 (simple 32-bit microcontroller without MMU) * ARC HS36 (advanced 32-bit microcontroller without MMU) * ARC HS38 (advanced 32-bit microcontroller with MMU) As a part of ARC HS38 new version of MMU (v4) was introduced. Also this change adds AXS131 board which is the same DW ARC SDP base board but with ARC HS38 CPU tile. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
generated by cgit v1.1 at 2024-11-18 03:03:43 +0000