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* x86: kconfig: Make FSP_TEMP_RAM_ADDR depend on HAVE_FSPBin Meng2015-06-04-0/+1
| | | | | | | FSP_TEMP_RAM_ADDR should only be visible when HAVE_FSP is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Adjust VGA initializationBin Meng2015-06-04-19/+17
| | | | | | | | | | | | | As VGA option rom needs to run at C segment, although QEMU PAM emulation seems to only guard E/F segments, for correctness, move VGA initialization after PAM decode C/D/E/F segments. Also since we already tested QEMU targets to differentiate I440FX and Q35 platforms, change to locate the VGA device via hardcoded b.d.f instead of dynamic search for its vendor id & device id pair. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Enable legacy IDE I/O ports decodeBin Meng2015-06-04-0/+38
| | | | | | | | | QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix driver does sanity check to see whether legacy ports decode is turned on. To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Turn on legacy segments decodeBin Meng2015-06-04-0/+26
| | | | | | | | | By default the legacy segments C/D/E/F do not decode to system RAM. Turn on the decode via Programmable Attribute Map (PAM) registers so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp_support: Correct high mem comment typoAndrew Bradford2015-06-04-1/+1
| | | | | | | | High mem starts at 4 GiB. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Do sanity test on pirq table before writingBin Meng2015-06-04-0/+3
| | | | | | | | | If pirq_routing_table points to NULL, that means U-Boot fails to generate the table before in create_pirq_routing_table(), so we test it against NULL before actually writing it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: quark: Implement PIRQ routingBin Meng2015-06-04-15/+123
| | | | | | | | | Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Refactor PIRQ routing supportBin Meng2015-06-04-300/+383
| | | | | | | | | | | | PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: qemu: Add graphics supportBin Meng2015-06-04-1/+23
| | | | | | | | It turns out that QEMU x86 emulated graphic card has a built-in option ROM which can be run perfectly with native mode by U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move FRAMEBUFFER_SET_VESA_MODE etc to video KconfigBin Meng2015-06-04-141/+0
| | | | | | | | | | CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE are not x86-specific, so move them to drivers/video/Kconfig and make them depend on VIDEO_VESA driver. Some cosmetic fixes are applied to the Kconfig help text as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Make QEMU the default vendorBin Meng2015-06-04-1/+1
| | | | | | | | | Now that we have QEMU support, make it the default vendor in the 'make menuconfig' screen. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* x86: Support QEMU x86 targetsBin Meng2015-06-04-1/+259
| | | | | | | | | | | This commit introduces the initial U-Boot support for QEMU x86 targets. U-Boot can boot from coreboot as a payload, or directly without coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig https://patchwork.ozlabs.org/patch/479745/
* Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-06-01-0/+26
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| * arm: rmobile: alt: Update to QoS revision 0.31 and 0.321Nobuhiro Iwamatsu2015-06-01-1/+5
| | | | | | | | | | | | | | | | This updates r8a7794 QoS to revision 0.31 for ES1 and revision 0.321 for ES2. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: gose: Update to QoS revision 0.311Nobuhiro Iwamatsu2015-06-01-1/+1
| | | | | | | | | | | | | | | | This updates r8a7793 QoS to revision 0.311. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: koelsch: Update to QoS revision 0.411Nobuhiro Iwamatsu2015-06-01-1/+1
| | | | | | | | | | | | | | | | This updates r8a7791 QoS to revision 0.411. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: lager: Update to QoS revision 0.973Nobuhiro Iwamatsu2015-06-01-0/+22
| | | | | | | | | | | | | | | | | | This updates r8a7790 QoS to revision 0.973. This commit can changed from KConfig to fit contents of the QoS. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-05-30-146/+98
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| * | ARM: UniPhier: add pin mux setting for NAND CS1 of PH1-Pro4Masahiro Yamada2015-05-31-0/+2
| | | | | | | | | | | | | | | | | | | | | The chip select 1 of the NAND controller is available if you want to use, although the pins are shared with UART port 2. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: fix pin mux setting for USB port 2 of PH1-sLD8Masahiro Yamada2015-05-31-2/+2
| | | | | | | | | | | | | | | | | | The register value should be 1, not 4. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: update DDR PHY register map for PH1-Pro5Masahiro Yamada2015-05-31-4/+7
| | | | | | | | | | | | | | | | | | | | | PH1-Pro5 includes a newer version of DDR PHY IP. Some registers have been added to the reserved areas. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: set MACH_PH1_PRO4 as default SoCMasahiro Yamada2015-05-31-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One disadvantage of commit a26cd04920dc (arch: Make board selection choices optional) is that Kconfig could create such an insane .config file that no board is selected. As PH1-Pro4 is the main stream of UniPhier SoC family, rip off the "optional" again in favor of PH1-Pro4 as the default SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: remove meaningless CONFIG_SPL_BUILD ifdefsMasahiro Yamada2015-05-31-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | This file is only built for SPL. These ifdef conditionals are unnecessary because UniPhier platform now supports UART on SPL. Show appropriate messages on error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: remove unnecessary cache coherency codeMasahiro Yamada2015-05-31-23/+1
| | | | | | | | | | | | | | | | | | | | | | | | Cache coherency for SMP is cared by Linux. In U-Boot, the secondary CPU(s) are just sleeping. Nothing in memory is shared with the primary CPU. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: use 32 bit register access for debug UART settingMasahiro Yamada2015-05-31-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | For the same reason as commit d0c47b3ef7c5 (serial: UniPhier: use 32 bit register access), use "str" instead of "strb" for the LCR register setting. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: update the vendor name of UniPhier in KconfigMasahiro Yamada2015-05-31-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The business for UniPhier Soc family has been transferred from Panasonic Corporation to Socionext Inc. Update the SoC select menu in Kconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: replace <asm/io.h> with <linux/io.h>Masahiro Yamada2015-05-31-104/+76
| |/ | | | | | | | | | | | | In the Linux coding style, it is recommended to include <linux/io.h> rather than <asm/io.h>. Follow this trend. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: sunxi: Share sun6i PSCI backend with sun8iChen-Yu Tsai2015-05-29-0/+5
| | | | | | | | | | | | | | | | | | sun8i can share the PSCI backend with sun6i. Only difference is sun8i does not have CPU power clamp controls. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: sunxi: Add sun6i specific PSCI implementationChen-Yu Tsai2015-05-29-0/+277
| | | | | | | | | | | | | | | | | | This adds PSCI support for sun6i. So far it only supports the PWR_ON method. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: sunxi: Make PSCI code sun7i specificChen-Yu Tsai2015-05-29-1/+1
| | | | | | | | | | | | | | | | | | | | | | The PSCI code only works for sun7i. Rename it with _sun7i suffix, and build only if building for sun7i. This paves the way for adding PSCI support for other platforms. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: sunxi: Document registers in PSCI codeChen-Yu Tsai2015-05-29-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | The PSCI CPU_ON code accesses quite a few registers. Document their names to make it easier to cross reference. Also explain "lock cpu" and "unlock cpu" as enabling/disabling debug access. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memoryDaniel Kochmański2015-05-29-2/+81
| | | | | | | | | | | | | | | | | | | | | | This commit adds support to the sunxi SPL to load u-boot from the internal NAND. Note this only adds support to access the boot partitions to load u-boot, full NAND support to load the kernel, etc. from the nand data partition will come later. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Match sun4i, sun6i, sun9i CCI definitions for NAND and DMARoy Spliet2015-05-29-3/+10
| | | | | | | | | | | | | | | | | | Make sure definitions for NAND clock and DMA gate bits are the same across boards. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add DMA definitionsRoy Spliet2015-05-29-0/+84
| | | | | | | | | | | | Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sun9i: Basic sun9i (A80) supportHans de Goede2015-05-29-0/+10
| | | | | | | | | | | | | | Add initial sun9i (A80) support, only uart + mmc are supported for now. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Remove support for building "old-fashioned" fel binariesHans de Goede2015-05-29-8/+0
| | | | | | | | | | | | | | | | | | | | The latest versions of the fel tool support loading normal u-boot builds directly, and this is now the preferred way to use the fel boot method. This commit removes support for the old deprecated standalone fel builds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Use axp221 sid on a33Hans de Goede2015-05-29-5/+3
|/ | | | | | | | | Unlike the A31 and the A23 the A33 actually has a SID inside the SoC again, but sid[3] is 0 (at least on some SoCs), so it is better to use the axp221 sid. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARMv7M: add STM32F1 supportMatt Porter2015-05-28-0/+782
| | | | | | Add ARMv7M STM32F1 support including clocks, timer, gpio, and flash. Signed-off-by: Matt Porter <mporter@konsulko.com>
* common/cmd_boot: keep ARM v7M in thumb mode during do_go_exec()Matt Porter2015-05-28-0/+45
| | | | | | | | On ARM v7M, the processor will return to ARM mode when executing a blx instruction with bit 0 of the address == 0. Always set it to 1 to stay in thumb mode. Signed-off-by: Matt Porter <mporter@konsulko.com>
* ARM: bcm283x: Switch to generic timerMarek Vasut2015-05-28-59/+1
| | | | | | | | | | | Switch to generic timer implementation from lib/time.c . This also fixes a signed overflow which was in __udelay() implementation. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tyler Baker <tyler.baker@linaro.org> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
* ARM: bcm283x: Reorder timer.hMarek Vasut2015-05-28-5/+10
| | | | | | | | Reorder the timer.h file so it can be included from board config file. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tyler Baker <tyler.baker@linaro.org>
* ARM: bcm283x: Repair wdog.hMarek Vasut2015-05-28-2/+2
| | | | | | | | Trivially fix the include check in wdog.h. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Tyler Baker <tyler.baker@linaro.org>
* powerpc: gitignore: ignore PowerPC DTBsMasahiro Yamada2015-05-28-0/+1
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-05-26-46/+202
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| * arm, imx6: add support for aristainetos2 boardHeiko Schocher2015-05-26-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add support for imx6dl based aristainetos2 board U-Boot 2015.04-rc5-00066-g60f6ed4 (Apr 10 2015 - 08:46:27) CPU: Freescale i.MX6DL rev1.1 at 792 MHz Reset cause: WDOG Board: aristaitenos2 Watchdog enabled I2C: ready DRAM: 1 GiB NAND: 1024 MiB MMC: FSL_SDHC: 0 SF: Detected N25Q128A with page size 256 Bytes, erase size 64 KiB, total 16 MiB Display: lg4573 (480x800) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 => Signed-off-by: Heiko Schocher <hs@denx.de>
| * i2c, mxc: rework i2c base address names for different SoCsHeiko Schocher2015-05-26-7/+7
| | | | | | | | | | | | | | rework and unify i2c address names for different SoCs, which use the mxc_i2c driver. Signed-off-by: Heiko Schocher <hs@denx.de>
| * arm, imx6, i2c: add I2C4 for MX6DLHeiko Schocher2015-05-26-12/+29
| | | | | | | | | | | | add I2C4 modul for MX6DL based boards. Signed-off-by: Heiko Schocher <hs@denx.de>
| * imx: dma: correct MXS_DMA_ALIGNMENTPeng Fan2015-05-26-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes. If on chips whose cache line size is 64 bytes, error occurs: " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * wandboard: Switch to SPL supportFabio Estevam2015-05-21-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently we need to build one U-boot image for each of the wandboard variants: quad, dual-lite and solo. By switching to SPL we can support all these variants with a single binary, which is very convenient. Based on the work from Richard Hu. Tested kernel booting on the three boards. Signed-off-by: Richard Hu <hakahu@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Tested-by: Vagrant Cascadian <vagrant@aikidev.net> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * imx: mx6: add display of CPU temperature grade in print_cpuinfo()Tim Harvey2015-05-19-4/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_IMX6_THERMAL is defined print the CPU temperature grade info along with the current temperature. Before: CPU: Temperature 42 C After: CPU: Automotive temperature grade (-40C to 125C) at 42C CPU: Industrial temperature grade (-40C to 105C) at 42C CPU: Extended Commercial temperature grade (-20C to 105C) at 42C Cc: Stefan Roese <sr@denx.de> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Heiko Schocher <hs@denx.de> Cc: Nikita Kiryanov <nikita@compulab.co.il> Cc: Jon Nettleton <jon.nettleton@gmail.com> Cc: Jason Liu <r64343@freescale.com> Cc: Ye Li <b37916@freescale.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Christian Gmeiner <christian.gmeiner@gmail.com> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Peng Fan <b51431@freescale.com> Tested-by: Nikolay Dimitrov <picmaster@mail.bg> Signed-off-by: Tim Harvey <tharvey@gateworks.com>
generated by cgit v1.1 at 2024-10-21 07:28:10 +0000