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* | arm: Remove omap3_sdp3430 boardSimon Glass2015-09-11-4/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove omap3_mvblx boardSimon Glass2015-09-11-4/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove nhk8815 boards and nomadik archSimon Glass2015-09-11-276/+0
| | | | | | | | | | | | | | These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove mx51_efikamx, mx51_efikasb boardsSimon Glass2015-09-11-5/+0
| | | | | | | | | | | | | | These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove mv88f6281gtw_ge boardSimon Glass2015-09-11-4/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove lp8x4x boardSimon Glass2015-09-11-5/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove jornada boardSimon Glass2015-09-11-5/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove mx31_litekit boardSimon Glass2015-09-11-5/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove imx27lite, imx27_litekit and magnesium boardsSimon Glass2015-09-11-9/+0
| | | | | | | | | | | | | | These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove ima3-mx53 boardSimon Glass2015-09-11-5/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove enbw_cmc boardSimon Glass2015-09-11-4/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove eb_cpu9k2 and eb_cpu9k2_ram boardsSimon Glass2015-09-11-5/+0
| | | | | | | | | | | | | | These board have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove dig297 boardSimon Glass2015-09-11-4/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove unmaintained davinci boardsSimon Glass2015-09-11-35/+3
| | | | | | | | | | | | | | | | These boards have not been converted to generic board by the deadline. Remove dm355evm, dm355leopard, dm365evm, dm6467evm, dvevm, ea20, schmoogie, sffsdr, sonata. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove snowball and u8500_href boardsSimon Glass2015-09-11-36/+0
| | | | | | | | | | | | | | These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove eukrea boardsSimon Glass2015-09-11-47/+0
| | | | | | | | | | | | | | These boards have not been converted to generic board by the deadline. Remove all cpu9260 and cpuat91 boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove balloon3 boardSimon Glass2015-09-11-18/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | ARM: DRA7: emif: Fix disabling/enabling of refreshesLokesh Vutla2015-09-11-3/+3
| | | | | | | | | | | | | | | | | | clrsetbits_le32/clrbits_le32 takes mask of the bits as input that are needed to be set/clear. But emif driver passes the shift of the bits. Fixing it here. Reported-by: Mark Mckeown <m-mckeown@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* | lpc32xx: remove duplicated DMA_CLK_ENABLE bit definitionVladimir Zapolskiy2015-09-11-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | Because there is an originally defined CLK_DMA_ENABLE macro in clk.h, no reason to add another DMA_CLK_ENABLE macro with the same value. Remove DMA_CLK_ENABLE, since it does not follow naming convention from the code, this implies renaming of DMA_CLK_ENABLE to CLK_DMA_ENABLE in lpc32xx/devices.c file. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-09-11-1/+1202
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| * | sun5i: Add A10s-Wobo-i5 defconfig and dtsJelle van der Waa2015-09-10-0/+236
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Wobo i5 top set box is a somewhat curious A10s based top set box, it uses an AXP209 rather then the AXP152 usually used in combination with the A10s. It has an ethernet phy connected to PORTD rather then PORTA, and its built-in usb wifi is connected via the otg controller. The dts file changes are identical to the changes submitted to the upstream kernel. Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sun5i: Add q8_a13_tablet defconfig and dtsHans de Goede2015-09-10-0/+308
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commits adds a generic support for q8 formfactor a13 based tablets. These tablets ship in many variants, with the difference mainly being the touchscreen controller / accelerometer / wifi chip used. The wifi is USB based, and thus not listed in devicetree. ATM the kernel does not support the touchscreen / accelerometer on these devices. In the future we may need multiple configs with different CONFIG_DEFAULT_DEVICE_TREE settings, this depends on how we solve the hw differences on the kernel side. For now this will suffice. The dts files are identical to the dts files submitted to the upstream kernel for these tablets. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sun4i: Add dts and defconfig for iNet-1 based tabletsHans de Goede2015-09-10-0/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The iNet-tek iNet-1 PCB is a PCB found in various generic 10.1" 1024x600 A10 based tablets such as the Point of View Protab2 XXL and the Cherry M1007. This patch has been tested on both rev2 and rev5 of this board / these tablets. These tablets feature the usual connectors: headphone, mini hdmi, power-barrel, mini-usb and a micro-sd slot. The dts is identical to the dts submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sun4i: Add defconfig and dts for inet9f-rev03 based tabletsHans de Goede2015-09-10-0/+220
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The inet9f-rev03 pcb is specially designed for gaming tablets, such as the qware tb-g100 tablet. These 7" tablets feature a dpad, firebuttons and 2 joysticks on the sides of the screen. Besides this they have the usual connectors: power-barrel, mini usb, mini hdmi, headphone and micro-sd slot. The dts is identical to the dts submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | sun4i: Add defconfig and dts for the pov protab2-ips9 tabletHans de Goede2015-09-10-1/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Point of View protab2-ips9 is a tablet with a 9" ips 1024x768 lcd screen, microsd slot, headphones, mini hdmi, mini usb b and power barrel connectors. The dts file is identical to the one submitted to the upstream kernel. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | | x86: quark: Add USB PHY initialization supportBin Meng2015-09-09-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | USB PHY needs to be properly initialized per Quark firmware writer guide, otherwise the EHCI controller on Quark SoC won't work. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Convert to use driver model pci on quark/galileoBin Meng2015-09-09-78/+6
| | | | | | | | | | | | | | | | | | | | | Move to driver model pci for Intel quark/galileo. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: Enable PCIe controller on quark/galileoBin Meng2015-09-09-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Quark SoC holds the PCIe controller in reset following a power on. U-Boot needs to release the PCIe controller from reset. The PCIe controller (D23:F0/F1) will not be visible in PCI configuration space and any access to its PCI configuration registers will cause system hang while it is held in reset. Enable PCIe controller per Quark firmware writer guide. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: quark: Avoid chicken and egg problemBin Meng2015-09-09-15/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we convert to use driver model pci on quark, we will encounter some chicken and egg problems like below: - To enable PCIe root ports, we need program some registers on the message bus via pci bus. With driver model, the first time to access pci bus, the pci enumeration process will be triggered. But without first enabling PCIe root ports, pci enumeration just hangs when scanning PCIe root ports. - Similar situation happens when trying to access GPIO from the PCIe enabling codes, as GPIO requires its block base address to be assigned via a pci configuration register in the bridge. To avoid such dilemma, replace all pci calls in the quark codes to use the local version which does not go through driver model. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: quark: Optimize MRC execution timeBin Meng2015-09-09-22/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel Quark SoC has a low end x86 processor with only 400MHz frequency. Currently it takes about 15 seconds for U-Boot to boot to shell and the most time consuming part is with MRC, which is about 12 seconds. MRC programs lots of registers on the SoC internal message bus indirectly accessed via pci bus. To speed up the boot, create an optimized version of pci config read/write dword routines which directly operate on PCI I/O ports. These two routines are inlined to provide better performance too. Now it only takes about 3 seconds to finish MRC, which is really fast (4 times faster than before). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | x86: coreboot: Convert to use more dm driversBin Meng2015-09-09-6/+0
| | | | | | | | | | | | | | | | | | | | | Move to driver model for RTC, USB and ETH on coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | | dm: test: Add a new test case for dm_test_eth_rotateBin Meng2015-09-09-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add one more ethernet device node in the sandbox test device tree, with name 'sbe5'. This is to support a new test case for testing network device rotation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | | x86: panther: Add PCI and video configurationSimon Glass2015-09-09-0/+10
|/ / | | | | | | | | | | | | | | | | Add a PCI node to the device tree. This allows SPI flash and SATA to work correctly. Also configure the video to come up correctly even though there is no keyboard. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-09-07-12/+241
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| * | arm: socfpga: Add support for the Terasic DE-0 Atlas boardDinh Nguyen2015-09-04-0/+69
| | | | | | | | | | | | | | | | | | | | | Add support for the Terasic DE0-Nano/Atlas-SoC Kit, which is a CycloneV based board. The board can boot from SD/MMC. Ethernet is also supported. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: Add support for DENX MCV SoM and MCVEVK boardMarek Vasut2015-09-04-0/+61
| | | | | | | | | | | | | | | | | | | | | | | | Add support for DENX MCV SoM, which is CycloneV based and the associated DENX MCVEVK baseboard. The board can boot from eMMC. Ethernet and USB is supported. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Add support for Terasic SoCkit boardMarek Vasut2015-09-04-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | Add support for Terasic SoCkit, which is CycloneV based board. The board can boot either from SD/MMC or QSPI. Ethernet is also supported. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Do not call board_init_r() from board_init_f()Marek Vasut2015-09-04-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of calling board_init_r() directly from board_init_f(), just return from board_init_f(). This will make the code continue executing in crt0.S _main(), from which the board_init_r() is called. This patch aligns the SoCFPGA SPL with the correct SPL design as well as reduces the stack utilisation slightly. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | arm: socfpga: Always enable OF_CONTROL and SPL_OF_CONTROLMarek Vasut2015-09-04-0/+2
| | | | | | | | | | | | | | | | | | | | | The SoCFPGA probes mostly from OF and the OF is mandatory both in U-Boot itself and U-Boot SPL. Enable it by default. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Assure ISWGRP 0 and 1 are initedMarek Vasut2015-09-04-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fix makes sure that the ISWGRP0 and ISWGRP1 registers are correctly inited. In case those registers are not initialized, it is not possible to access the registers synthesised in the FPGA through the bridges. Any such access produces data abort. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | mmc: dw_mmc: Probe the MMC from OFMarek Vasut2015-09-04-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rework the driver to probe the MMC controller from Device Tree and make it mandatory. There is no longer support for probing from the ancient qts-generated header files. This patch now also removes previous temporary workaround. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Tom Rini <trini@konsulko.com>
* | | arc: make AXS101 default platformAlexey Brodkin2015-09-07-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes building in automated flow that doesn't use defconfigs. See discussion on that topic here: http://patchwork.ozlabs.org/patch/502558/ See similar patches for other architectures/platforms here: [1] http://git.denx.de/?p=u-boot.git;a=commit;h=ff560a13056a565a4e9ce1761bd04276a3cace88 [2] http://git.denx.de/?p=u-boot.git;a=commit;h=589907e2c187ec69b351c38ccda36730d25ab5d6 And while at it add missing shell prompt to axs103. Cc: Tom Rini <trini@konsulko.com> Cc: Joe Hershberger <joe.hershberger@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2015-09-03-6/+6636
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| * | arm: Turn of d-cache before i-cacheSjoerd Simons2015-09-02-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting the kernel fails on RK3288 (and probably other rockchip SoCs) when the i-cache is disabled/flushed before d-cache. I have not investigated whether this is due to U-Boot hanging or whether it's very early in the linux boot, but following the approach of the various rockchip U-Boot forks (first disable d-cache then i-cache) makes things work. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Disable sdio mmc slot on rk3288-fireflySjoerd Simons2015-09-02-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot can't use the sdio card so turn it of to prevent things getting confused/struck when trying to use the card as storage. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add basic support for jerrySimon Glass2015-09-02-1/+1275
| | | | | | | | | | | | | | | | | | This builds and displays an SPL message, but does not function beyond that. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add basic support for firefly-rk3288Simon Glass2015-09-02-0/+544
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Firefly RK3288 is a suitable target board for initial mainline Rockchip support. It includes a good set of peripherals, a recent SoC and it is readily available. This adds only some basic files required to allow the baord to display a serial message in SPL and hang. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add SPI driverSimon Glass2015-09-02-0/+20
| | | | | | | | | | | | | | | | | | | | | Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add I2C driverSimon Glass2015-09-02-0/+70
| | | | | | | | | | | | | | | | | | | | | Add an I2C driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add core SoC start-up codeSimon Glass2015-09-02-0/+432
| | | | | | | | | | | | | | | | | | | | | Add code for starting up U-Boot SPL and U-Boot proper. This is generic and makes use of devices provided by the board- or SoC-specific code. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit v1.1 at 2024-11-13 16:34:49 +0000