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| * x86: Add support for U-Boot as an EFI applicationBen Stoltz2015-08-05-0/+319
| | | | | | | | | | | | | | | | | | | | Add the required x86 glue code. This includes the initial start-up, relocation and jumping to efi_main(). We also need to avoid fiddling with interrupts. Signed-off-by: Ben Stoltz <stoltz@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add asm/elf.h for x86-specific ELF definitionsSimon Glass2015-08-05-0/+46
| | | | | | | | | | | | | | | | Bring in this file from Linux 4.1. It supports relocation features specific to x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Support skipping relocation for EFISimon Glass2015-08-05-0/+6
| | | | | | | | | | | | | | | | When running as an EFI application we must skip relocation. Add support for this in the x86 relocation code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Set up toolchain flags for running as EFI applicationBen Stoltz2015-08-05-3/+27
| | | | | | | | | | | | | | | | | | | | Adjust the toolchain flags to build U-Boot as a relocatable shared library, as required by EFI. Signed-off-by: Ben Stoltz <stoltz@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * efi: Add start-up library codeSimon Glass2015-08-05-57/+2
| | | | | | | | | | | | | | | | | | | | | | When running as an EFI application, U-Boot must request memory from EFI, and provide access to the boot services U-Boot needs. Add library code to perform these tasks. This includes efi_main() which is the entry point from EFI. U-Boot is built as a shared library. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Allow use of global_data with EFISimon Glass2015-08-05-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On x86 the global_data pointer is provided through a somewhat-bizarre and x86-specific mechanism: the F segment register is set to a pointer to the start of global_data, so that accesses can use this build-in register. When running as an EFI application we don't want to mess with the Global Descriptor Table (GDT) and there is little advantage (in terms of code size) to doing so. Allow global_data to be a simple variable in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up a few minor issues with interruptsSimon Glass2015-08-05-5/+4
| | | | | | | | | | | | | | | | Fix a typo, remove an unused field and make sure to use existing #define constants instead of open-coded values. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add some missing global_data declarations in files that use gdSimon Glass2015-08-05-0/+10
| | | | | | | | | | | | | | Some files use global_data but don't declare it. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up the 64-bit calling codeSimon Glass2015-08-05-2/+2
| | | | | | | | | | | | | | | | The GDT works but technically the length is incorrect. Fix this and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Drop unused copy_fdt_to_ram()Simon Glass2015-08-05-19/+0
| | | | | | | | | | | | | | | | This is now handled by generic U-Boot code so we do not need an x86 version. It is no-longer called, so remove it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Tidy up global_data flagsSimon Glass2015-08-05-7/+11
| | | | | | | | | | | | | | | | | | | | These flags now overlap some global ones. Adjust the x86-specific flags to avoid this. Since this requires a change to the start.S code, add a way for tools to find the 32-bit cold reset entry point. Previously this was at a fixed offset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Use CR0 constants in CPU initSimon Glass2015-08-05-1/+1
| | | | | | | | | | | | | | We should use these constants where possible. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add various minor tidy-ups to the 32-bit startup codeSimon Glass2015-08-05-20/+26
| | | | | | | | | | | | | | | | Fix a typo, improve some comments and add a little more detail in some cases. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: bayleybay: Configure PCI IRQBin Meng2015-08-05-0/+71
| | | | | | | | | | | | | | | | Add PCI IRQ routing information in the board device tree and enable writing PIRQ routing table and MP table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add Intel Bayley Bay board supportBin Meng2015-08-05-1/+136
| | | | | | | | | | | | | | | | Intel Bayley Bay board is a BayTrail based board. Add this board with existing baytrail fsp support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add microcode for BayTrail-I B0 steppingBin Meng2015-08-05-0/+4244
| | | | | | | | | | | | | | | | This commit adds the microcode blob for BayTrail-I B0 stepping, CPUID signature 30671h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Update UPD setting for FSP Gold4 releaseBin Meng2015-08-05-1/+2
| | | | | | | | | | | | | | | | BayTrail FSP Gold4 release adds one UPD parameter to control IGD enable/disable. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: qemu: Add MP initializationBin Meng2015-08-05-0/+14
| | | | | | | | | | | | | | | | | | Add a cpu1 node to the device tree and enable the MP initialization on QEMU targets (i440fx and q35). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * x86: Add a 'pause' instruction in __udelay() for QEMU targetMiao Yan2015-08-05-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running SMP configuration on QEMU (tcg mode, no kvm), there is a busy loop in start_aps(), calling udelay(), that waits for APs to show up online. However, there is a chance that VCPU1 will be timeout waiting, IOW the secondary VCPUs haven't started their execution yet. This patch adds a 'pause' instruction in __udelay() only for QEMU target, to give other VCPUs a chance to run. When QEMU sees the 'pause' instruction, it will yeild the execution to other CPUs. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | sunxi: Drop our own copy of the USB_KEYBOARD optionsHans de Goede2015-08-05-0/+1
| | | | | | | | | | | | | | USB_KEYBOARD is now defined in drivers/usb/Kconfig, drop our own duplicate definition. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | usb: musb-new: CONFIG_MUSB prefix replacement with CONFIG_USB_MUSBPaul Kocialkowski2015-08-05-2/+2
|/ | | | | | | | | USB-related options are usually prefixed with CONFIG_USB and platform-specific adaptation for the MUSB controller already have a CONFIG_USB_MUSB prefix, so this switches all MUSB-related options to a CONFIG_USB_MUSB prefix, for consistency. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* armv8/lsch3/config: Define USB XHCI controller base address for LS2085ANikhil Badola2015-08-03-0/+3
| | | | | | | | Define base address of both usb xhci controllers in lsch3 config in the format (IMMR + offset) for LS2085A Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv8/lsch3/config: Define CONFIG_SYS_CACHELINE_SIZE for LS2085ANikhil Badola2015-08-03-0/+1
| | | | | | | | Define CONFIG_SYS_CACHELINE_SIZE for LS2085A which is required by USB XHCI stack for alignment Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* armv7/ls102xa: Fix non-boot cpus cannot correctly fall in spin tableWang Dongsheng2015-08-03-0/+8
| | | | | | | | | | | Bootrom will put cpus into WFE state when boot cpu release cpus, so target cpu cannot correctly go to spin state. Add 'sev' to wakeup non-boot cpu that hold on bootrom space, let target cpu can fall into u-boot spin table. Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-08-02-218/+1776
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| * imx: mx6ul_14x14_evk add basic board supportPeng Fan2015-08-02-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add USDHC, I2C, UART, 74LV, USB, QSPI support. 2. Support SPL 3. CONFIG_MX6UL_14X14_EVK_EMMC_REWORK is introduced, this board default supports sd for usdhc2, but can do hardware rework to make usdhc2 support emmc. Boot Log: U-Boot SPL 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59) reading u-boot.img reading u-boot.img U-Boot 2015.07-rc3-00124-g35d727b (Jul 20 2015 - 18:40:59 +0800) CPU: Freescale i.MX6UL rev1.0 792 MHz (running at 396 MHz) CPU: Commercial temperature grade (0C to 95C)CPU: Thermal invalid data, fuse: 0x0 - invalid sensor device Reset cause: POR Board: MX6UL 14x14 EVK I2C: ready DRAM: 512 MiB MMC: FSL_SDHC: 0, FSL_SDHC: 1 *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Net: CPU Net Initialization Failed No ethernet found. Hit any key to stop autoboot: 0 Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx:mx6ul add dram spl configuration and header filePeng Fan2015-08-02-10/+141
| | | | | | | | | | | | | | | | | | | | | | | | 1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs. 2. Add a new function mx6ul_dram_iocfg to configure dram io. 3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support runtime check, but not hardcoding #ifdef macros. 4. Introduce mx6ul-ddr.h, which includes the register address for DRAM IO configuration. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/ULPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | | | PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6) Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul update soc related settingsPeng Fan2015-08-02-5/+4
| | | | | | | | | | | | | | | | 1.Update WDOG settings. 2.No need to gate/ungate all PFDs for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * imx: mx6ul select SYS_L2CACHE_OFFPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | | | | | | | i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6 chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled. There is on specific switch for on/off L2 Cache, so default select SYS_L2CACHE_OFF. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx:mx6ul add clock supportPeng Fan2015-08-02-90/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add enet, uart, i2c, ipg clock support for i.MX6UL. 2. Correct get_periph_clk, it should account for MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK. 3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function, but not use 'ifdef'. 4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX. 5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q) || defined....", only need one CONFIG_PCIE_IMX in header file. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx-common: timer: add i.MX6UL supportPeng Fan2015-08-02-3/+5
| | | | | | | | | | | | Add i.MX6UL GPT timer support. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6ULPeng Fan2015-08-02-0/+4
| | | | | | | | | | | | | | Since i.MX6UL's cache line size is 64bytes, need to define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul: Update imx registers head filePeng Fan2015-08-02-25/+35
| | | | | | | | | | | | | | | | | | | | | | | | 1. Update imx register base address for i.MX6UL. 2. Remove duplicated MXS_APBH/GPMI/BCH_BASE. 3. Remove #ifdef for register addresses that equal to "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips. 4. According fuse map, complete fuse_bank4_regs. 5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX, because we can use runtime check Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * imx: mx6ul: Add pins IOMUX head filePeng Fan2015-08-02-0/+1067
| | | | | | | | | | | | | | Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * imx: mx6ul: Add i.MX6UL CPU typePeng Fan2015-08-02-1/+4
| | | | | | | | | | | | | | | | | | | | Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which is not real id from DIGPROG register, so change i.MX6D to value 0x67 which was not occupied. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * arm: mx6: kconfig: don't select CPU_V7 per boardNikita Kiryanov2015-08-02-3/+0
| | | | | | | | | | | | | | | | | | | | CPU_V7 is already selected by ARCH_MX6, so no point in selecting it again by boards that depend on ARCH_MX6. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
| * arm: mx6: cm-fx6: move cm-fx6 target under ARCH_MX6Nikita Kiryanov2015-08-02-8/+8
| | | | | | | | | | | | | | | | | | | | cm-fx6 is an MX6 based board, and the menuconfig hierarchy should reflect that. Make TARGET_CM_FX6 dependant on ARCH_MX6. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
| * imx: mx6qp Enable PRG clock for IPUPeng Fan2015-08-02-0/+5
| | | | | | | | | | | | | | | | | | | | The i.MX6DQP has a PRG module, need to enable its clock for using IPU. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Brown Oliver <B37094@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QPYe.Li2015-08-02-1/+2
| | | | | | | | | | | | | | | | | | Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: mx6: ccm: Change the clock settings for i.MX6QPPeng Fan2015-08-02-34/+49
| | | | | | | | | | | | | | | | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. In c files, use runtime check and discard #ifdef. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * imx: add cpu type for i.MX6QP/DPPeng Fan2015-08-02-5/+16
| | | | | | | | | | | | | | | | | | | | | | Add cpu type for i.MX6QP/DP. This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP and MXC_CPU_MX6DP, we should use: (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-07-17-627/+1798
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| * | i2c: fix vf610 supportAlbert ARIBAUD \(3ADEV\)2015-07-10-4/+15
| | | | | | | | | | | | | | | | | | | | | Add support in mxc_i2c driver, iomux_v3 and vf610 architecture for the four I2C instances available in VF610. Signed-off-by: Albert ARIBAUD (3ADEV) <albert.aribaud@3adev.fr>
| * | iMX: adding parsing to hab_status commandUlises Cardenas2015-07-10-13/+245
| | | | | | | | | | | | | | | | | | | | | | | | hab_status command returns a memory dump of the hab event log. But the raw data is not human-readable. Parsing such data into readable event will help to minimize debbuging time. Signed-off-by: Ulises Cardenas <Ulises.Cardenas@freescale.com>
| * | imx: mx6 add i2c4 clock support for i.MX6SXPeng Fan2015-07-10-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C4 clock support for i.MX6SX. Since we use runtime check, but not macro, we need to remove `#ifdef ..` in crm_regs.h, or gcc will fail to compile the code succesfully. Making the macros only for i.MX6SX open to other i.MX6x maybe not a good choice, but we have runtime check. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * | imx: mx6 remove duplicated enable_cspi_clockPeng Fan2015-07-10-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | enable_spi_clock does the same thing with enable_cspi_clock, so remove enable_cspi_clock. Remove enable_cspi_clock prototype in header file convert cm_fx6/spl.c to use enable_spi_clk Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-07-31-58/+89
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| * | | powerpc/t4240: update serdes tableShaohui Xie2015-07-31-55/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Serdes Lanes availability on T4160 and T4080 are same, which serdes 2 & 3 support 8 Lanes, but serdes 1 & 4 support only 4 Lanes E/F/G/H, Lanes A/B/C/D are not available, updated the serdes table accordingly with some minor fix. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | powerpc/mpc85xx: SECURE BOOT-Copy Boot Script on RAMAneesh Bansal2015-07-31-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For running Chain of Trust when doing Secure Boot from NAND, the Bootscript header and bootscript must be copied from NAND to RAM(DDR). The addresses and commands for the same have been defined. Signed-off-by: Saksham Jain <saksham@freescale.com> Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
generated by cgit v1.1 at 2024-11-16 04:55:58 +0000