summaryrefslogtreecommitdiff
path: root/arch
Commit message (Collapse)AuthorAgeLines
* rockchip: Use rockchip_get_clk() to obtain the SoC clockSimon Glass2016-07-25-3/+3
| | | | | | | | | | | | The current code picks the first available clock. In U-Boot proper this is the oscillator device, not the SoC clock device. As a result the HDMI display does not work. Fix this by calling rockchip_get_clk() instead. Fixes: 135aa950 (clk: convert API to match reset/mailbox style) Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
* rockchip: Add a way to obtain the main clock deviceSimon Glass2016-07-25-0/+20
| | | | | | | | On Rockchip SoCs we typically have a main clock device that uses the Soc clock driver. There is also a fixed clock for the oscillator. Add a function to obtain the core clock. Signed-off-by: Simon Glass <sjg@chromium.org>
* cosmetic: rockchip: rk3288: rename rkclk_configure_cpuHeiko Stübner2016-07-25-2/+2
| | | | | | | | | | The function is very specific to the rk3288 in its arguments referencing the rk3288 cru and grf and every other rockchip soc has differing cru and grf registers. So make that function naming explicit. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Simon Glass <sjg@chromium.org>
* cosmetic: rockchip: sort socs according to numbersHeiko Stübner2016-07-25-12/+12
| | | | | | | | | | Having some sort of ordering proofed helpful in a lot of other places already. So for a larger number of rockchip socs it might be helpful as well instead of an ever increasing unsorted list. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: rk3288: add fastboot supportXu Ziyuan2016-07-25-0/+73
| | | | | | | | | | | | Enable fastboot feature on rk3288. This path doesn't support the fastboot flash function command entirely. We will hit "cannot find partition" assertion without specified partition environment. Define gpt partition layout in specified board such as firefly-rk3288, then enjoy it! Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Exclude rk_timer for ARM64Andreas Färber2016-07-25-0/+2
| | | | | | | | It conflicts with the generic_timer. Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
* rockchip: Clean up CPU selectionAndreas Färber2016-07-25-1/+2
| | | | | | | | | In preparation for RK3368 and RK3399, which need to select ARM64, don't select CPU_V7 at the ARCH_ROCKCHIP level but at the SoC level instead. Cc: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Simon Glass <sjg@chromium.org>
* board: move all the rockchip board in one folderKever Yang2016-07-25-2/+2
| | | | | | | | | | | The 'evb_rk3036' and 'kylin' is not a vendor name, let's replace them to 'rockchip' which is a real _vendor_ name, and meet the architecure 'board/<vendor>/<board-name>/'. More boards from rockchip like evb_rk3288, evb_rk3399 will comes later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Eddie Cai <eddie.cai.kernel@gmail.com>
* rockchip: add basic support for evb-rk3288 boardXu Ziyuan2016-07-25-1/+451
| | | | | | | | | | | | | | evb-3288 board RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet. It also includes on-board 8G eMMC and 2GB of SDRAM. Expansion connector provide access to display pins, I2C, SPI, UART and GPIOs. This add some basic files required to allow the board to output serial messaged and can run command(mmc info etc). evb-rk3288 also supports booting from eMMC or SD card, the default is eMMC. Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* rockchip: add option to change method of loading u-bootXu Ziyuan2016-07-25-3/+47
| | | | | | | | | | | | | | | | | If we would like to boot from SD card, we have to implement mmc driver in SPL stage, and get a slightly large SPL binary. Rockchip SoC's bootrom code has the ability to load spl and u-boot, then boot. If CONFIG_ROCKCHIP_SPL_BACK_TO_BROM is enabled, the spl will return to bootrom in board_init_f(), then bootrom loads u-boot binary. Loading sequence after rework: bootrom ==> spl ==> bootrom ==> u-boot Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Fixed up spelling of U-Boot, boorom, opinion->option, Rochchip: Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-nand-flashTom Rini2016-07-25-0/+98
|\
| * sunxi: Enable NAND controller on the CHIPBoris Brezillon2016-07-24-0/+44
| | | | | | | | | | | | | | Enable the NAND controller in the sun5i-r8-chip.dts. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
| * sun5i: Add NAND controller to the sun5i DTSIMaxime Ripard2016-07-24-0/+49
| | | | | | | | | | | | | | Add the NAND controller definition to sun5i.dtsi. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * sunxi: Add missing macros to configure the NAND controller clkBoris Brezillon2016-07-24-0/+5
| | | | | | | | | | | | | | We need some macros to manipulate the NAND controller clock. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: am33xx: Always inhibit init/refresh during DDR phy initRuss Dill2016-07-25-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A couple of commits have modified the am33xx/am437x ddr2/ddr3 initialization path to fix certain issues, but have had the side effect of causing L3 noc errors during initialization. The two commits are: 69b918 "am33xx,ddr3: fix ddr3 sdram configuration" fc46ba "arm: am437x: Enable hardware leveling for EMIF" The EMIF_REG_INITREF_DIS_MASK bit still needs to be set for all platforms. This delays initialization and refresh until a later stage. The 500us timer can be programmed for platforms that require it and for platforms that don't require it. It is currently hardcoded for 400MHz systems. For systems with a higher memory frequency this needs to be a larger value, and for systems with a lower memory frequency this can be a lower value. This can be considered a separate issue and corrected in a later commit. Signed-off-by: Russ Dill <Russ.Dill@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: am33xx: Fix DDR init delay placementRuss Dill2016-07-25-1/+4
| | | | | | | | | | | | | | | | | | The delay needs to be before the write to ref_ctrl register which initiates refreshes. An improper initialization sequence generates an L3 noc error. Signed-off-by: Russ Dill <Russ.Dill@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | keystone: k2h/e/l: Fix DMA coherency for QM PDSPKaricheri, Muralidharan2016-07-25-2/+0
|/ | | | | | | | | | | | | | commit 1f807a9f32aa ("ARM: keystone2: Refactor MSMC macros to avoid left under a macro KS2_MSMC_SEGMENT_QM_PDSP which is no longer valid. This, in effect disabled DMA coherency for QM PDSP. Given that msmc_k2hkle_common_setup is valid for all K2H/K/L/E SoCs, the #ifdef should been removed in the first place. Do the same. Fixes: 1f807a9f32aa ("ARM: keystone2: Refactor MSMC macros to avoid #ifdeffery") Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: uniphier: add clock/reset settings for xHCI of ProXstream2Masahiro Yamada2016-07-24-2/+13
| | | | | | | Deassert resets and enable clock signals of xHCI blocks if the corresponding CONFIG is enabled. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add PH1-LD21 board dataMasahiro Yamada2016-07-24-0/+19
| | | | | | | This has the same silicon die as PH1-LD20, but includes DRAM chips in its package. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: introduce flags to uniphier_board_data structureMasahiro Yamada2016-07-24-11/+20
| | | | | | | I need to add more board attributes, so the "flags" member will be handier than separate boolean ones. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: rename outer-cache register macrosMasahiro Yamada2016-07-24-216/+230
| | | | | | | Sync register macros with Linux code. This will be helpful to develop the counterpart of Linux. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: clear notification flag before L2 operationMasahiro Yamada2016-07-24-6/+6
| | | | | | | Clear the flag immediately before cache operation to not depend on the previous state. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: use (devm_)ioremap() instead of map_sysmem()Masahiro Yamada2016-07-24-21/+19
| | | | | | | | This does not have much impact on behavior, but makes code look more more like Linux. The use of devm_ioremap() often helps to delete .remove callbacks entirely. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: select CONFIG_ARMV8_SPIN_TABLEMasahiro Yamada2016-07-23-0/+1
| | | | | | This is needed when booting Linux without ARM Trusted Firmware. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: renumber serial aliases for Gentil/Vodka boardsMasahiro Yamada2016-07-23-8/+8
| | | | | | | | | | | | On these two boards, the serial0 is used for inter-chip connection, so cannot be used for login console. The serial2 is used instead for them, but it is tedious to use because upper level deployment projects must switch login console per board. [ Linux commit: 2a4a2aadbaad9dffdb564a2895348f3d8e825416 ] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Olof Johansson <olof@lixom.net>
* arm: omap5: fix build dependency for secure devicesAndreas Dannenberg2016-07-22-1/+1
| | | | | | | | | | | Commit 17c2987 introduces an undesired dependency on CONFIG_SPL_LOAD_FIT when building U-Boot for AM57xx and DRA7xx high-security (HS) devices that causes the build to break when that option is not active. Fix this issue by only building the u-boot_HS.img target when building U-Boot into an actual FIT image. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: am4x: fix build dependency for secure devicesAndreas Dannenberg2016-07-22-1/+1
| | | | | | | | | | | Commit e29878f introduces an undesired dependency on CONFIG_SPL_LOAD_FIT when building U-Boot for AM43xx high-security (HS) devices that causes the build to break when that option is not active. Fix this issue by only building the u-boot_HS.img target when building U-Boot into an actual FIT image. Signed-off-by: Andreas Dannenberg <dannenberg@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* armv8: spl: Call board_init_r from crt0_64 in SPLJeremy Hunt2016-07-22-15/+12
| | | | | | | | | | | | | | | As part of the startup process for boards using the SPL, the meaning of board_init_f changed such that it should return normally rather than calling board_init_r directly. (see db910353a126d84fe8dff7a694ea792f50fcfb6a ) This was fixed in 32-bit arm, but broke when SPL was added to 64 bit arm. This fixes crt0_64 so that it calls board_init_r during the SPL and removes the direct call from board_init_f from the arm SPL example. Signed-off-by: Jeremy Hunt <Jeremy.Hunt@DEShawResearch.com> Acked-by: Simon Glass <sjg@chromium.org>
* armv7: simplify identify_nand_chipLadislav Michl2016-07-22-24/+11
| | | | | | Use newly introduced function Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* armv7: armv7: introduce set_gpmc_cs0Ladislav Michl2016-07-22-58/+91
| | | | | | Allow boards to runtime detect flash type. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* armv7: make gpmc_cfg constLadislav Michl2016-07-22-9/+6
| | | | | | | | Signed-off-by: Ladislav Michl <ladis@linux-mips.org> [trini: Adapt am33xx, duovero, omap_zoom1] Signed-off-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* armv7: add reset timeout to identify_nand_chipLadislav Michl2016-07-22-19/+15
| | | | | | | | | | identify_nand_chip hangs forever in loop when NAND is not present. As IGEPv2 comes either with NAND or OneNAND flash, add reset timeout to let function fail gracefully allowing caller to know NAND is not present. On NAND equipped board, reset succeeds on first read, so 1000 loops seems to be safe timeout. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* spl: zImage support in Falcon modeLadislav Michl2016-07-22-32/+42
| | | | | | | | Other payload than uImage is currently considered to be raw U-Boot image. Check also for zImage in Falcon mode. Signed-off-by: Ladislav Michl <ladis@linux-mips.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2016-07-22-18/+3
|\
| * ARM64: zynqmp: Remove get_uart_clk()Michal Simek2016-07-22-17/+0
| | | | | | | | | | | | ZynqMP will use reading clock freq directly from DT. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * ARM64: zynqmp: Enable CLK and SPL_CLK by defaultMichal Simek2016-07-22-0/+2
| | | | | | | | | | | | | | Serial driver starts to use clk framework that's why enable it by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * spl: Fix compilation warnings for arm64Michal Simek2016-07-22-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make code 64bit aware. Warnings: +../arch/arm/lib/spl.c: In function ‘jump_to_image_linux’: +../arch/arm/lib/spl.c:63:3: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] +../common/spl/spl_fat.c: In function ‘spl_load_image_fat’: +../common/spl/spl_fat.c:91:33: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2016-07-21-7/+66
|\ \
| * | powerpc/mpc85xx: T104x: Add nand secure boot targetSumit Garg2016-07-21-6/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For mpc85xx SoCs, the core begins execution from address 0xFFFFFFFC. In non-secure boot scenario from NAND, this address will map to CPC configured as SRAM. But in case of secure boot, this default address always maps to IBR (Internal Boot ROM). The IBR code requires that the bootloader(U-boot) must lie in 0 to 3.5G address space i.e. 0x0 - 0xDFFFFFFF. For secure boot target from NAND, the text base for SPL is kept same as non-secure boot target i.e. 0xFFFx_xxxx but the SPL U-boot binary will be copied to CPC configured as SRAM with address in 0-3.5G(0xBFFC_0000) As a the virtual and physical address of CPC would be different. The virtual address 0xFFFx_xxxx needs to be mapped to physical address 0xBFFx_xxxx. Create a new PBI file to configure CPC as SRAM with address 0xBFFC0000 and update DCFG SCRTACH1 register with location of Header required for secure boot. The changes are similar to commit 467a40dfe35f48d830f01a72617207d03ca85b4d powerpc/mpc85xx: SECURE BOOT- NAND secure boot target for P3041 While P3041 has a 1MB CPC and does not require SPL. On T104x, CPC is only 256K and thus SPL framework is used. The changes are only applicable for SPL U-Boot running out of CPC SRAM and not the next level U-Boot loaded on DDR. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc/mpc85xx: SECURE BOOT- Enable chain of trust in SPLSumit Garg2016-07-21-1/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-07-21-25/+886
|\ \ \ | |_|/ |/| |
| * | ARM: tegra: pick up actual memory sizeStephen Warren2016-07-21-12/+110
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Tegra186, U-Boot is booted by the binary firmware as if it were a Linux kernel. Consequently, a DTB is passed to U-Boot. Cache the address of that DTB, and parse the /memory/reg property to determine the actual RAM regions that U-Boot and subsequent EL2/EL1 SW may actually use. Given the binary FW passes a DTB to U-Boot, I anticipate the suggestion that U-Boot use that DTB as its control DTB. I don't believe that would work well, so I do not plan to put any effort into this. By default the FW-supplied DTB is the L4T kernel's DTB, which uses non-upstreamed DT bindings. U-Boot aims to use only upstreamed DT bindings, or as close as it can get. Replacing this DTB with a DTB using upstream bindings is physically quite easy; simply replace the content of one of the GPT partitions on the eMMC. However, the binary FW at least partially relies on the existence/content of some nodes in the DTB, and that requires the DTB to be written according to downstream bindings. Equally, if U-Boot continues to use appended DTBs built from its own source tree, as it does for all other Tegra platforms, development and deployment is much easier. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: Add save_boot_params for ARMv8Stephen Warren2016-07-21-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement a hook to allow boards to save boot-time CPU state for later use. When U-Boot is chain-loaded by another bootloader, CPU registers may contain useful information such as system configuration information. This feature mirrors the equivalent ARMv7 feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: add IVC protocol implementationStephen Warren2016-07-21-0/+742
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IVC (Inter-VM Communication) protocol is a Tegra-specific IPC (Inter Processor Communication) framework. Within the context of U-Boot, it is typically used for communication between the main CPU and various auxiliary processors. In particular, it will be used to communicate with the BPMP (Boot and Power Management Processor) on Tegra186 in order to manipulate clocks and reset signals. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: unify Tegra186 Makefile a bitStephen Warren2016-07-21-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many files in arch/arm/mach-tegra are compiled conditionally based on Kconfig variables, or applicable to all platforms. We can let the main Tegra Makefile handle compiling (or not) those files to avoid each SoC- specific Makefile needing to duplicate entries for those files. This leaves the SoC-specific Makefiles to compile truly SoC-specific code. In the future, we'll hopefully add Kconfig variables for all the other files, and refactor those files, and so reduce the need for SoC-specific Makefiles and/or ifdefs in the Makefiles. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: split p2771-0000 buildStephen Warren2016-07-21-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are multiple versions of p2771-0000 board. There are SW visible incompatible differences between the versions, and they are relevant to U-Boot. Create separate "A02" and "B00" defconfigs (named after the first and/or only board rev the defconfig supports) so that users can select which build they want. With the minimal set of HW currently enabled in U-Boot, the differences are irrelevant, hence the DT files aren't different. However, that will change in a future patch. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: fix Tegra186 DT GPIO binding headerStephen Warren2016-07-21-1/+1
| |/ | | | | | | | | | | | | | | Tegra186 uses different GPIO port IDs compared to previous chips. Make sure the SoC DT file includes the correct GPIO binding header. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Revert "stm32: Change USART port to USART6 for stm32f746 discovery board"Tom Rini2016-07-21-5/+0
|/ | | | | | | | | | Per Vikas' request, the problem this commit is supposed to be solving is something he doesn't see and further this introduces additional hardware requirements. This reverts commit 4b2fd720a7b2f78c42d1565edf4c67f378c65440. Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-07-19-583/+994
|\ | | | | | | | | | | | | | | Signed-off-by: Tom Rini <trini@konsulko.com> Conflicts: arch/arm/cpu/armv8/Makefile arch/arm/lib/bootm-fdt.c
| * ARMv8/PSCI: Fixup the device tree for PSCIHou Zhiqiang2016-07-19-64/+159
| | | | | | | | | | | | | | | | Set the enable-method in the cpu node to PSCI, and create device node for PSCI, when PSCI was enabled. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
generated by cgit v1.1 at 2024-11-10 23:56:50 +0000