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* ARM: uniphier: compile board data only for SPLMasahiro Yamada2017-01-29-1/+1
| | | | | | | Now U-Boot proper need not get the uniphier_boards array. Compile it only for SPL. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor cmd_ddrmphyMasahiro Yamada2017-01-29-83/+112
| | | | | | Make it look like cmd_ddrphy. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: clean up UMC init for PXs2 SoCMasahiro Yamada2017-01-29-283/+284
| | | | | | | | | Just cosmetic changes: - Rename prefix DMPHY_ to MPHY_ for consistency - Move UMC parameters below for complete decouple of PHY and UMC - Remove redundant whitespaces Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: refactor cmd_ddrphyMasahiro Yamada2017-01-29-73/+83
| | | | | | | It seems more readable to use arrays to get SoC specific parameters instead of the crappy switch statement. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: use gd->bd->bi_dram for memory reserve on LD20 SoCMasahiro Yamada2017-01-29-10/+3
| | | | | | | | | | For LD20 SoC, the last 64 byte of each DRAM bank is used for the dynamic training of DRAM PHY. The regions must be reserved in DT to prevent the kernel from using them. Now gd->bd->bi_dram reflects the actual memory banks. Just use it instead of getting access to the board parameters. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: detect RAM size by decoding HW register instead of DTMasahiro Yamada2017-01-29-49/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot needs to set up available memory area(s) in dram_init() and dram_init_banksize(). It is platform-dependent how to detect the memory banks. Currently, UniPhier adopts the memory banks _alleged_ by DT. This is based on the assumption that users bind a correct DT in their build process. Come to think of it, the DRAM controller has already been set up before U-Boot is entered (because U-Boot runs on DRAM). So, the DRAM controller setup register seems a more reliable source of any information about DRAM stuff. The DRAM banks are initialized by preliminary firmware (SPL, ARM Trusted Firmware BL2, or whatever), so this means the source of the reliability is shifted from Device Tree to such early-stage firmware. However, if the DRAM controller is wrongly configured, the system will crash. If your system is running, the DRAM setup register is very likely to provide the correct DRAM mapping. Decode the SG_MEMCONF register to get the available DRAM banks. The dram_init() and dram_init_banksize() need similar decoding. It would be nice if dram_init_banksize() could reuse the outcome of dram_init(), but global variables are unavailable at this stage because the .bss section is available only after the relocation. As a result, SG_MEMCONF must be checked twice, but a new helper uniphier_memconf_decode() will help to avoid code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: shrink arrays of DDR-PHY parameters for LD20 SoCMasahiro Yamada2017-01-29-175/+79
| | | | | | | | | | | | | The two arrays ddrphy_{op,ip}_dq_shift_val, occupy more than 3.8 KB memory footprint, which is significant in SPL. There are PHY parameters for 5 boards, but they are actually not board specific, but SoC specific. After all, we just need to have 2 patterns, for LD20 and LD21. Also, the shift values are small enough to become "short" type instead of "int". This change will save about 3 KB memory footprint. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: SPI: stm32: add stm32f746 qspi driverMichael Kurz2017-01-28-2/+8
| | | | | | This patch adds support for the QSPI IP found in stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com>
* net: stm32: add designware mac glue code for stm32Michael Kurz2017-01-28-0/+44
| | | | | | | | This patch adds glue code required for enabling the designware mac on stm32f7 devices. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* ARM: stm32: use clock setup function defined in clock.cMichael Kurz2017-01-28-28/+14
| | | | | | | | | | | Use the clock setup function defined in clock.c instead of setting the clock bits directly in the drivers. Remove register definitions of RCC in rcc.h as these are already defined in the struct in stm32.h Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
* ARM: stm32: fix stm32f7 sdram fmc base addressMichael Kurz2017-01-28-3/+2
| | | | | | | | | The fmc base address is defined twice, once in fmc.h and once in stm32.h. Fix wrong definition in stm32.h. Remove the definiton in fmc.h. Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas Manocha <vikas.manocha@st.com>
* ARM: stm32: cleanup stm32f7 filesMichael Kurz2017-01-28-118/+110
| | | | | | | | | | | | Cleanup stm32f7 files: - use BIT macro - use GENMASK macro - use rcc struct instead of macro additions Add missing stm32f7 register in rcc struct Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA<vikas.manocha@st.com>
* ARM: DTS: stm32: add stm32f746-disco device tree filesMichael Kurz2017-01-28-0/+202
| | | | | | | | | | | This patch adds the DTS source files needed for stm32f746-disco board The files are based on the stm32f429/469 files from current linux kernel. Source for "arch/arm/dts/armv7-m.dtsi": Linux: "arch/arm/boot/dts/armv7-m.dtsi" Signed-off-by: Michael Kurz <michi.kurz@gmail.com> Acked-by: Vikas MANOCHA <vikas.manocha@st.com>
* arm: omap3: Update cpuinfo for DM3730, DM3725, AM3715, and AM3703Adam Ford2017-01-28-2/+48
| | | | | | | | | | | | The check for OMAP3630/3730 only checks for 800MHz 3630/3730, but anything else is lumped into 36XX/37XX with an assumed 1GHz speed. Based on the DM3730 TRM bit 9 shows the MPU Frequency (800MHz/1GHZ). This also adds the ability to distinguish between the DM3730, DM3725, AM3715, and AM3703 and correctly display their maximum speed. Signed-off-by: Adam Ford <aford173@gmail.com> Tested-by: Ladislav Michl <ladis@linux-mips.org>
* arm: omap3: Fix cpuinfo frequency spellingLadislav Michl2017-01-28-3/+3
| | | | | | Frequency is measured in Hz. Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
* arm64: spin-table: add more information in Kconfig helpMasahiro Yamada2017-01-28-2/+4
| | | | | | | | | | | | | | | | | | | | | This feature seems to be sometimes misunderstood. The intention is: [1] Bring the slaves into the U-Boot proper image, not SPL (unless you have a special reason to do otherwise). [2] The operation must be done in a board (SoC) specific manner since how to wake the slaves from the Boot ROM is SoC specific. [3] The slaves must enter U-Boot proper after U-Boot relocates itself because the "cpu-release-addr" property points to the relocated memory area. [2] is already explained in the help. We can make [1] even clearer by mentioning "U-Boot proper" instead of "U-Boot". [3] is missing, so I am adding it to the list. Instead, "before the master CPU jumps to the kernel" is a matter of course, so removed. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* board/chiliboard: Add support for chiliBoardMarcin Niestroj2017-01-28-0/+8
| | | | | | | | | | | | | chiliBoard is a development board which uses chiliSOM as its base. Hardware specification: * chiliSOM (TI AM335x, DRAM, NAND) * Ethernet PHY (id 0) * USB host (usb1) * MicroSD slot (mmc0) Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: am335x: Add support for chiliSOMMarcin Niestroj2017-01-28-0/+206
| | | | | | | | | | | | | | | | | chiliSOM is a System On Module (http://http://grinn-global.com/chilisom/). It can't exists on its own, but will be used as part of other boards. Hardware specification: * TI AM335x processor * 128M, 256M or 512M DDR3 memory * up to 256M NAND We place source inside arch/arm/mach-omap2/ directory and make it possible to reuse initialization code (i.e. DDR, NAND init) for all boards that use it. Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* aspeed: Support for ast2500 Eval Boardmaxims@google.com2017-01-28-0/+27
| | | | | ast2500 Eval Board device tree and board specific configuration. Reviewed-by: Simon Glass <sjg@chromium.org>
* aspeed: Board init functions and common configs for ast2500 based boardsmaxims@google.com2017-01-28-1/+84
| | | | | | | | Add configuration file with parameters that are very likely to be shared by all ast2500-based boards. Add ast2500-board.c file with the init code that is very likely to be shared by all ast2500-based boards. Reviewed-by: Simon Glass <sjg@chromium.org>
* aspeed: Add basic ast2500-specific drivers and configurationmaxims@google.com2017-01-28-0/+970
| | | | | | | | | | | | | | | | | | | | | Clock Driver This driver is ast2500-specific and is not compatible with earlier versions of this chip. The differences are not that big, but they are in somewhat random places, so making it compatible with ast2400 is not worth the effort at the moment. SDRAM MC driver The driver is very ast2500-specific and is completely incompatible with previous versions of the chip. The memory controller is very poorly documented by Aspeed in the datasheet, with any mention of the whole range of registers missing. The initialization procedure has been basically taken from Aspeed SDK, where it is implemented in assembly. Here it is rewritten in C, with very limited understanding of what exactly it is doing. Reviewed-by: Simon Glass <sjg@chromium.org>
* aspeed: Add drivers common to all Aspeed SoCsmaxims@google.com2017-01-28-0/+254
| | | | | | | | | | | | | | | | | Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
* arm: Re-sync with full list of MACH_TYPE_xxx valuesTom Rini2017-01-28-1/+4064
| | | | | | | This re-syncs us with the official and full list of MACH_TYPE_xxx values from http://www.armlinux.org.uk/developer/machines/ Signed-off-by: Tom Rini <trini@konsulko.com>
* disk: convert CONFIG_DOS_PARTITION to KconfigPatrick Delaunay2017-01-28-2/+0
| | | | | Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay73@gmail.com>
* Merge git://www.denx.de/git/u-boot-marvellTom Rini2017-01-26-0/+67
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| * arm64: mvebu: Armada 7040-db: Add SDHCI device tree nodesStefan Roese2017-01-25-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SDHCI device tree nodes to the Armada 7040-db dts file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
| * arm64: mvebu: Armada 7k/8k: Add SDHCI device tree nodesStefan Roese2017-01-25-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SDHCI device tree nodes to the Armada AP806 dtsi file which is used by the Armada 7k/8K SoCs. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
| * arm64: mvebu: Armada 3720-db: Add SDHCI device tree nodesStefan Roese2017-01-25-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SDHCI device tree nodes to the Armada 3700-db dts file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
| * arm64: mvebu: Armada 3700: Add SDHCI device tree nodesStefan Roese2017-01-25-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the SDHCI device tree nodes to the Armada 3700 dtsi file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Wilson Ding <dingwei@marvell.com> Cc: Victor Gu <xigu@marvell.com> Cc: Hua Jing <jinghua@marvell.com> Cc: Terry Zhou <bjzhou@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Cc: Haim Boot <hayim@marvell.com>
* | Merge git://git.denx.de/u-boot-mpc85xxTom Rini2017-01-25-3/+30
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| * | powerpc: Enable flush and invalidate dcache by range for MPC85xxTony O'Brien2017-01-24-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-ops for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues in some drivers when the dcache was flushed. While the root cause was under investigation, these functions were disabled in Commit cb1629f91a for affected SoCs, including the MPC85xx, to make the various drivers work. On the T208x USB stopped working after v2016.07 was pulled. After re-enabling the dcache functions for the MPC85xx it started working again. The USB and DPPA Ethernet drivers have been seen as operational after this change but other drivers cannot be tested. Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> Cc: Marek Vasut <marex@denx.de> Cc: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun>
| * | mpc85xx: pcie: Implement workaround for Erratum A007815Tony O'Brien2017-01-24-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The read-only-write-enable bit is set by default and must be cleared to prevent overwriting read-only registers. This should be done immediately after resetting the PCI Express controller. Reviewed-by: Hamish Martin <hamish.martin@alliedtelesis.co.nz> Signed-off-by: Tony O'Brien <tony.obrien@alliedtelesis.co.nz> [York S: Move SYS_FSL_ERRATUM_A007815 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
| * | powerpc: mpc85xx: Implemente workaround for CPU erratum A-007907Darwin Dingel2017-01-24-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Core hang occurs when using L1 stashes. Workaround is to disable L1 stashes so software uses L2 cache for stashes instead. Reviewed-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Darwin Dingel <darwin.dingel@alliedtelesis.co.nz> Cc: York Sun <york.sun@nxp.com> [York S: Move SYS_FSL_ERRATUM_A007907 to Kconfig] Reviewed-by: York Sun <york.sun@nxp.com>
* | | Drop prt_mpc5xxx_clks() in favour of print_cpuinfo()Simon Glass2017-01-25-1/+1
| | | | | | | | | | | | | | | | | | | | | Rather than having an arch-specific function, use the existing generic one. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | powerpc: Drop CONFIG_SYS_ALLOC_DPRAMSimon Glass2017-01-25-126/+7
| | | | | | | | | | | | | | | | | | This is not defined anywhere in U-Boot. Drop this dead code. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | powerpc: Drop probecpu() in favour of arch_cpu_init()Simon Glass2017-01-25-1/+1
| | | | | | | | | | | | | | | | | | | | | To avoid an unnecessary arch-specific call in board_init_f(), rename this function. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Convert CONFIG_ARCH_MISC_INIT to KconfigSimon Glass2017-01-25-2/+9
| | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_ARCH_MISC_INIT Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Convert CONFIG_BOARD_EARLY_INIT_F to KconfigSimon Glass2017-01-25-0/+63
| | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_BOARD_EARLY_INIT_F Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Convert CONFIG_ARCH_EARLY_INIT_R to KconfigSimon Glass2017-01-25-1/+6
| | | | | | | | | | | | | | | | | | | | | This converts the following to Kconfig: CONFIG_ARCH_EARLY_INIT_R Signed-off-by: Simon Glass <sjg@chromium.org>
* | | config: Drop CONFIG_ARCH_DMA_PIO_WORDSSimon Glass2017-01-25-6/+1
| |/ |/| | | | | | | | | This is not defined by any board in U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mach-omap2: Cleanup secure boot media generationAndrew F. Davis2017-01-24-10/+28
| | | | | | | | | | | | | | | | | | | | Currently all secure media types of SPL are generated for all platforms, all platforms do not need all types, only generate the media types valid for each platform. Signed-off-by: Andrew F. Davis <afd@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Tested-by: Lokesh Vutla <lokeshvutla@ti.com>
* | Kconfig: Migrate BOARD_LATE_INIT to a selectTom Rini2017-01-24-0/+144
| | | | | | | | | | | | | | | | | | This option should not really be user selectable. Note that on PowerPC we currently only need BOARD_LATE_INIT when CHAIN_OF_TRUST is enabled so be conditional on that. Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> (for UniPhier)
* | NXP: Introduce board/freescale/common/Kconfig and migrate CHAIN_OF_TRUSTTom Rini2017-01-24-13/+0
| | | | | | | | | | | | | | | | | | Introduce board/freescale/common/Kconfig so that we have a single place for CONFIG options that are shared between ARM and PowerPC NXP platforms. Cc: York Sun <york.sun@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | imx31_phycore: Split the eet variant out into a different TARGETTom Rini2017-01-24-1/+5
|/ | | | | | | Rename CONFIG_IMX31_PHYCORE_EET to CONFIG_TARGET_IMX31_PHYCORE_EET and make this a distinct config target. Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: uniphier: add PXs3 SoC supportMasahiro Yamada2017-01-22-0/+27
| | | | | | Initial support for PXs3 SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add PXs3 SoC/board supportMasahiro Yamada2017-01-22-0/+381
| | | | | | Initial commit for the PXs3 SoC DT. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: compile only DT files that make senseMasahiro Yamada2017-01-22-9/+18
| | | | | | | | | All the UniPhier DT files are compiled if CONFIG_ARCH_UNIPHIER is enabled, but not all of them actually work. For example, when U-Boot is compiled for ARM 32 bit, 64 bit DT files are also built, and vice versa. Compile only the combination that makes sense. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add macro to generate SoC data look-up functionMasahiro Yamada2017-01-22-33/+23
| | | | | | | | There are similar functions that look up SoC data by the SoC ID. The new macro UNIPHIER_DEFINE_SOCDATA_FUNC will be helpful to avoid the code duplication. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: simplify SoC ID get functionMasahiro Yamada2017-01-22-317/+214
| | | | | | | | | | Currently, uniphier_get_soc_type() converts the SoC ID (this is read from the revision register) to an enum symbol to use it for SoC identification. Come to think of it, there is no need for the conversion in the first place. Using the SoC ID from the register as-is a straightforward way. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: replace <common.h> with <linux/delay.h> where possibleMasahiro Yamada2017-01-22-4/+5
| | | | | | | | | The <common.h> includes too many headers. Actually, these files needed to include it for udelay() declaration. Now we can replace it with <linux/delay.h> thanks to commit 5bc516ed661a ("delay: collect {m, n, u}delay declarations to include/linux/delay.h"). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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