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* ARM: at91: clock: complete the GCK's clock sourcesWenyou Yang2016-05-24-0/+8
| | | | | | | | Add the UPLL clock and master clock as a clock source for getting the generated clock frequency to complete its clock sources support. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* ARM: at91: clock: fix the GCK's clock sourceWenyou Yang2016-05-24-0/+5
| | | | | | | | Before enabling a generated clock whose source is from the UPLL clock, check and enable the UPLL clock. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* board: atmel: add SAMA5D2 PTC Engineering boardWenyou Yang2016-05-24-0/+6
| | | | | | | | | | The board supports following features: - Boot media support: NAND Flash/SPI Flash - Support ethernet - Support USB mass storage Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* ARM: at91: sama5d2: add macro & field definitionsWenyou Yang2016-05-24-0/+29
| | | | | | | They will be used on SAMA5D2 PTC board. Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas@biessmann.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-05-23-20/+4386
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| * malta: Support MIPS32r6 configurationsPaul Burton2016-05-21-0/+1
| | | | | | | | | | | | | | | | Both real Malta boards & QEMU's Malta emulation can feature MIPS32r6 CPUs. Allow building U-Boot for such systems by selecting CONFIG_SUPPORTS_CPU_MIPS32_R6 for Malta. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Support for targetting MIPSr6Paul Burton2016-05-21-6/+30
| | | | | | | | | | | | | | | | | | | | | | Add support for targetting MIPS32r6 & MIPS64r6 systems, in the same way that we currently select release 1 or release 2 targets. MIPSr6 is not entirely backwards compatible with earlier releases of the architecture. Some instructions are encoded differently, some are removed, some are reused, so it is not practical to run U-Boot built for earlier revisions on a MIPSr6 system. Update their Kconfig help text to reflect that. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Simplify CONFIG_SYS_CPU valuesPaul Burton2016-05-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Rather than having the values for CONFIG_SYS_CPU depend upon each architecture revision, have them depend upon the more general CONFIG_CPU_MIPS32 & CONFIG_CPU_MIPS64 which in turn depend upon the architecture revisions. This is done in preparation for adding MIPSr6 support, which would otherwise need to introduce new cases here. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * MIPS: Use unchecked immediate addition/subtractionPaul Burton2016-05-21-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | In MIPS assembly there have historically been 2 variants of immediate addition - the standard "addi" which traps if an overflow occurs, and the unchecked "addiu" which does not trap on overflow. In release 6 of the MIPS architecture the trapping variants of immediate addition & subtraction have been removed. In preparation for supporting MIPSr6, stop using the trapping instructions from assembly & switch to their unchecked variants. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
| * mips: ath79: Add support for TPLink WDR4300Marek Vasut2016-05-21-0/+59
| | | | | | | | | | | | | | | | | | | | Add support for the TPLink WDR4300 router, which is based on the AR9344 MIPS 74Kc CPU and has 128 MiB of RAM. The USB is supported on this system as well. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: Add AR934x supportMarek Vasut2016-05-21-1/+683
| | | | | | | | | | | | | | | | | | | | Add support for the Atheros AR934x WiSoCs. This patchs adds complete system init, including PLL and DRAM init, both of which happen from full C environment, since the AR934x has proper SRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: Add support for ungating ethernet on ar933x and ar934xMarek Vasut2016-05-21-0/+80
| | | | | | | | | | | | | | | | Add code to ungate the ethernet controller on ar933x and ar934x . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: dts: Add ethernet MAC nodes for ar933xMarek Vasut2016-05-21-0/+26
| | | | | | | | | | | | | | | | | | Add node for both ethernet controllers in the ar933x. The PHY is attached only to the first ethernet controller. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: Add support for ungating USB on ar933x and ar934xMarek Vasut2016-05-21-0/+61
| | | | | | | | | | | | | | | | Add code to ungate the USB controller on ar933x and ar934x . Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: dts: Add generic-ehci nodeMarek Vasut2016-05-21-0/+7
| | | | | | | | | | | | | | | | Add generic EHCI node for the ChipIdea EHCI controller in the ath79. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: Fix compiler warning on const assignmentMarek Vasut2016-05-21-1/+1
| | | | | | | | | | | | | | | | | | The assignment const T var; var = value; is illegal, since var is constant. Drop the const to fix the compiler warning. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: ath79: Fix ar71xx_regs.h indentMarek Vasut2016-05-21-1034/+1069
| | | | | | | | | | | | | | | | | | The indent in this file triggers my OCD, so fix it. Replace multiple spaces with tabs and align the values in one column. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com>
| * mips: Add MIPS 74Kc tuneMarek Vasut2016-05-21-0/+4
| | | | | | | | | | | | | | | | | | | | Add MIPS 74Kc tune Kconfig option. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Wills Wang <wills.wang@live.com> [added missing tune-y entry in arch/mips/Makefile] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: Fix compiler warning in cpu.cMarek Vasut2016-05-21-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There really is zero reason for including netdev.h in generic mips CPU code. Removing the netdev.h from cpu.c also fixes the following compiler warning: In file included from arch/mips/cpu/cpu.c:10:0: include/netdev.h:204:41: warning: 'struct eth_device' declared inside parameter list [enabled by default] int fecmxc_register_mii_postcall(struct eth_device *dev, int (*cb)(int)); ^ include/netdev.h:204:41: warning: its scope is only this definition or declaration, which is probably not what you want [enabled by default] Signed-off-by: Marek Vasut <marex@denx.de> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * ath79: add readonly attribute for ath79_soc_descWills Wang2016-05-21-4/+4
| | | | | | | | | | | | use 'const' keywork to qualify readonly attribute for lookup-table member Signed-off-by: Wills Wang <wills.wang@live.com>
| * ath79: ar933x: use BIT macro for bit shift operationWills Wang2016-05-21-7/+7
| | | | | | | | | | | | used a uniform BIT macro for register bit-field shift Signed-off-by: Wills Wang <wills.wang@live.com>
| * mips: ath79: add AP143 reference boardWills Wang2016-05-21-0/+133
| | | | | | | | | | | | | | | | This patch add board-level code and base DT for AP143. Signed-off-by: Wills Wang <wills.wang@live.com> [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: ath79: add AP121 reference boardWills Wang2016-05-21-0/+137
| | | | | | | | | | | | | | | | This patch add board-level code and base DT for AP121. Signed-off-by: Wills Wang <wills.wang@live.com> [updated defconfig, enabled CONFIG_USE_PRIVATE_LIBGCC=y] Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * mips: ath79: add support for QCA953x SOCsWills Wang2016-05-21-1/+787
| | | | | | | | | | | | This patch enable work for qca953x SOC. Signed-off-by: Wills Wang <wills.wang@live.com>
| * mips: ath79: add support for AR933x SOCsWills Wang2016-05-21-0/+720
| | | | | | | | | | | | This patch enable work for ar933x SOC. Signed-off-by: Wills Wang <wills.wang@live.com>
| * mips: add base support for QCA/Atheros ath79 SOCsWills Wang2016-05-21-0/+1610
| | | | | | | | | | | | | | This patch add some common code for QCA/Atheros ath79 SOCs such as DDR tuning, chip reset and CPU detection. Signed-off-by: Wills Wang <wills.wang@live.com>
* | ARM: fix ifdef in ARMv8 lowlevel_init() againMasahiro Yamada2016-05-23-1/+1
|/ | | | | | | | | Commit 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()") accidentally inverted the logic of CONFIG_ARMV8_MULTIENTRY. Fixes: 116611937faa ("ARM: fix ifdefs in ARMv8 lowlevel_init()") Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2016-05-17-53/+175
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| * dm: scsi: Rename CONFIG_CMD_SCSI to CONFIG_SCSISimon Glass2016-05-17-1/+1
| | | | | | | | | | | | | | | | This option currently enables both the command and the SCSI functionality. Rename the existing option to CONFIG_SCSI since most of the code relates to the feature. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: Add string and 16-bit I/O functionsSimon Glass2016-05-17-0/+15
| | | | | | | | | | | | | | | | | | | | Add outsw() and insw() functions for sandbox, as these are needed by the IDE code. The functions will not do anything useful if called, but allow the code to be compiled. Also add out16() and in16(), required by systemace. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: Rename disk uclass to ahciSimon Glass2016-05-17-4/+7
| | | | | | | | | | | | | | | | This started as 'ahci' and was renamed to 'disk' during code review. But it seems that this is too generic. Now that we have a 'blk' uclass, we can use that as the generic piece, and revert to ahci for this. Signed-off-by: Simon Glass <sjg@chromium.org>
| * dm: spi: soft_spi: switch to use linux compatible stringPeng Fan2016-05-17-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Support compatible string "spi-gpio" which is used by Linux Linux use different bindings, so use UBOOT_COMPAT and LINUX_COMPAT to differentiate them. 2. Introduce SPI_MASTER_NO_RX and SPI_MASTER_NO_TX to handle no rx or no tx case. 3. Tested on i.MX6 UltraLite board with 74LV595 spi-gpio chip. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * video: tegra: refuse to bind to disabled dcsStephen Warren2016-05-17-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This prevents the following boot-time message on any board where only the first DC is in use, yet the DC's DT node is enabled: stdio_add_devices: Video device failed (ret=-22) (This happens on at least Harmony, Ventana, and likely any other Tegra20 board with display enabled other than Seaboard). The Tegra DC's DT node represents a display controller. It may itself drive an integrated RGB display output, or be used by some other display controller such as HDMI. For this reason the DC node itself is not enabled/disabled in DT; the DC itself is considered a shared resource, not the final (board-specific) display output. The node should instantiate a display output driver only if the rgb subnode is enabled. Other output drivers are free to use the DC if they are enabled and their DT node references the DC's DT node. Adapt the Tegra display drivers' bind() routine to only bind to the DC's DT node if the RGB subnode is enabled. Now that the display driver does the right thing, remove the workaround for this issue from Seaboard's DT file. Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * m68k: add malloc memory for early mallocangelo@sysam.it2016-05-17-39/+147
| | | | | | | | | | | | | | | | | | To use serial uclass and DM, CONFIG_SYS_MALLOC_F must be used. So CONFIG_SYS_GENERIC_GLOBAL_DATA has been undefined and call to board_init_f_mem() is added for all cpu's. Signed-off-by: Angelo Dureghello <angelo@sysam.it> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2016-05-17-6/+7
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| * | imx: imx-common: print i.MX 7 SoC names consistentlyStefan Agner2016-05-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | According to the product website, the full names are i.MX 7Solo and i.MX 7Dual, whereas the short form is i.MX7S and i.MX7D. Be consistent and print the short form for both supported i.MX 7 SoCs. Signed-off-by: Stefan Agner <stefan@agner.ch> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
| * | imx: imx7d: fix ahb clock mux 1Stefan Agner2016-05-17-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock parent of the AHB root clock when using mux option 1 is the SYS PLL 270MHz clock. This is specified in Table 5-11 Clock Root Table of the i.MX 7Dual Applications Processor Reference Manual. While it could be a documentation error, the 270MHz parent is also mentioned in the boot ROM configuration in Table 6-28: The clock is by default at 135MHz due to a POST_PODF value of 1 (=> divider of 2). Signed-off-by: Stefan Agner <stefan@agner.ch>
| * | imx: iomux-v3: fix UART input selectsStefan Agner2016-05-17-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several UART input selects are missing. The fourth input select for UART2_TX_DATA_ALT0 is actually also missing in the documentation. (at least in Rev. B of the i.MX 7Dual Reference Manual). However, when looking at the tables of other input selects, it is very natural that there must be an input select for the UART2_TX_DATA_ALT0 pad. The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and it was required to set that particular input select register to get a working UART2.
| * | imx: mx6: mx6sl_pins: add GPIO variant for SD1_DAT5Eric Nelson2016-05-17-0/+1
| |/ | | | | | | | | | | | | This patch adds the IOMUX setting for using SD1_DAT5 as GPIO5:9. Signed-off-by: Eric Nelson <eric@nelint.com> Reviewed-by: Peng Fan <van.freenix@gmail.com>
* | dm: fsl_i2c: Enable DM for FSL I2Cmario.six@gdsys.cc2016-05-17-0/+10
| | | | | | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* | dm: fsl_i2c: Rename I2C register structuremario.six@gdsys.cc2016-05-17-6/+6
|/ | | | Signed-off-by: Mario Six <mario.six@gdsys.cc>
* arm/arm64: Move barrier instructions into separate headerAndre Przywara2016-05-12-21/+46
| | | | | | | | | | | | | | | | Commit bfb33f0bc45b ("sunxi: mctl_mem_matches: Add missing memory barrier") broke compilation for the Pine64, as dram_helper.c now includes <asm/armv7.h>, which does not compile on arm64. Fix this by moving all barrier instructions into a separate header file, which can easily be shared between arm and arm64. Also extend the inline assembly to take the "sy" argument, which is optional for ARMv7, but mandatory for v8. This fixes compilation for 64-bit sunxi boards (Pine64). Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-05-06-1/+2
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| * socfpga: fix broken build if CONFIG_ETH_DESIGNWARE disabledAnatolij Gustschin2016-05-06-1/+1
| | | | | | | | | | | | | | Building without ethernet driver doesn't work. Fix it. Signed-off-by: Anatolij Gustschin <agust@denx.de> Cc: Marek Vasut <marex@denx.de>
| * ARM: socfpga: Disable USB OC protection on SoCratesMarek Vasut2016-05-06-0/+1
| | | | | | | | | | | | | | | | This is mandatory, otherwise the USB does not work. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Dinh Nguyen <dinguyen@kernel.org>
* | imx6: cache: disable L2 before touching Auxiliary Control RegisterPeng Fan2016-05-06-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According PL310 TRM, Auxiliary Control Register " The register must be written to using a secure access, and it can be read using either a secure or a NS access. If you write to this register with a NS access, it results in a write response with a DECERR response, and the register is not updated. Writing to this register with the L2 cache enabled, that is, bit[0] of L2 Control Register set to 1, results in a SLVERR. " So If L2 cache is already enabled by ROM, chaning value of ACR will cause SLVERR and uboot hang. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
* | ARM: am33xx: Fix DDR initialization delaysRuss Dill2016-05-06-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current delays in the DDR initialization routines for am33xx architectures are sometimes not running long enough leading to DDR init errors. On am437x, this shows up as an L3 NOC error after the kernel boots. This is due to the timer not being initialized properly, but instead still containing the timer init values from the boot ROM which cause timers to expire in 1/4th the time required. timer_init is typically not called until board_init_r, however on am33xx/am43xx udelay is required in sdram_init which is called from board_init_f, so a call to timer_init is required earlier. Note that this issue introduced in v2015.01 by: b352dde "am33xx: Drop timer_init call from s_init". Although this could instead fixed by reverting said commit, it would cause timer_init to be called twice in both SPL and non-SPL cases. This gives a little more fine grained control and also matches what is being done on omap-command and fsl-layerscape. Signed-off-by: Russ Dill <russ.dill@ti.com>
* | ARM: fix ifdefs in ARMv8 lowlevel_init()Stephen Warren2016-05-06-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 724219a65f55 "ARM: always perform per-CPU GIC init" removed some ifdefs to unify the MULTIENTRY-vs-non-MULTIENTRY paths. However, the wrong endif was removed. This patch adds back that missing endif, and adds a new ifdef to match the endif the now-correctly-terminated block used to match against. Use "git show -U25 724219a65f55" to see enough context to make the original issue clear. In practical terms, this makes no difference to runtime behaviour. The code that was incorrectly compiled into the binary when ifndef MULTIENTRY is a no-op for other cases, since branch_if_master evaluates to a hard- coded jump. The only issues were: - A few extra instructions were added to the binary. - The comment on the endif at the very end of the function, indicating which ifdef it matched, were wrong. An alternative might be to simply fix the comment on that trailing ifdef, but that only addresses the second point above, not the first. Fixes: 724219a65f55 ("ARM: always perform per-CPU GIC init") Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Fix various typos, scattered over the code.Robert P. J. Day2016-05-05-4/+4
|/ | | | | | | | | | | | | Spelling corrections for (among other things): * environment * override * variable * ftd (should be "fdt", for flattened device tree) * embedded * FTDI * emulation * controller
* ARM: tegra: enable GPU node by compatible valueStephen Warren2016-05-04-15/+22
| | | | | | | | | | | | | | | | | | | In current Linux kernel Tegra DT files, 64-bit addresses are represented in unit addresses as a pair of comma-separated 32-bit values. Apparently this is no longer the correct representation for simple busses, and the unit address should be represented as a single 64-bit value. If this is changed in the DTs, arm/arm/mach-tegra/board2.c:ft_system_setup() will no longer be able to find and enable the GPU node, since it looks up the node by name. Fix that function to enable nodes based on their compatible value rather than their node name. This will work no matter what the node name is, i.e for DTs both before and after any rename operation. Cc: Thierry Reding <treding@nvidia.com> Cc: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
generated by cgit v1.1 at 2024-11-15 21:53:12 +0000